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Claude 68a9493572 Vector types (SIMD): f32x8, i8x32, f64x4 and the rest; --cpu native ... - fNxM / iNxM / uNxM up to 512 bits, as LLVM vectors (<8 x float>): LLVM picks SSE, AVX2, AVX-512 or NEON for them - f32x8(x) in every lane, f32x8(a, ..., h), f32x8(list, i) loads, f32x8(i32x8 v) converts - + - * / and the bit operators lane by lane, with a plain number on either side counting for every lane; v[i], v[i] = x, v.len, == / != (every lane), print and str - methods: sum min max dot abs sqrt floor ceil round fma store; min/max/abs/clamp lane by lane - wide vectors (and structs holding them) are loaded and stored with align 16, what malloc and the stack give - --cpu <name> (and cpu = "..." in finch.toml): native, x86-64-v3, apple-m1, ... - debug info shows vectors; the language server completes their methods; Kate and VS Code highlight them - f32 x = -1.5 works: a minus in front of a float written in the code keeps it such a number Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01Psc42moPLwP43Cmb9oZqSR		2026-11-01 13:50:35 +00:00
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finch.tmLanguage.json	Vector types (SIMD): f32x8, i8x32, f64x4 and the rest; --cpu native	2026-11-01 13:50:35 +00:00