Linux's own r8169 through LDLS, deep idle, and the GPU plan
The RTL8168 is now driven by Linux's r8169, unmodified, in a process. `make ldls-r8169` stages it from the running kernel together with libphy, mdio-bus, mdio_devres and the Realtek PHY driver, the kernel's BTF and the RTL PHY firmware, and etc/schinit/ldls-r8169.job starts it at boot with its log in /var/log/ldls-r8169.log. The native driver is out of the registry; its code, now with Linux's 8168H setup, stays as the fallback. LDLS grows what that needed: - ldlsd loads a comma-separated module set in dependency order, each linking against the ones before it, with BTF read before any init_module runs; - a driver core (bus match, driver probe), devres, kernel printf, real udelay/msleep/ktime and 1000 Hz jiffies, phylib's bitmaps and link_mode_params, firmware from /lib/firmware, and the symbols whose stub zero was a lie (list validity, try_module_get, dev_err_probe, eth_platform_get_mac_address); - pdev->bus is a real pci_bus, and cmovcc from per-CPU memory is rewritten like the other %gs forms. In QEMU all five modules load, link and initialise, and r8169 registers and finds no device. Probe and traffic are untested until real hardware. The kernel turns ASPM off on Realtek NIC links at boot, as r8169 does through pci_disable_link_state, which a process cannot. Idle CPUs enter ACPI _CST's C2 (CC6 on Zen) by port read or MWAIT when the APIC timer keeps running, instead of only ever halting at C1. docs/plan/gpu.md: amdgpu and nouveau through LDLS, with measurements. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01S1giNvrHTrPMPw7V6x1kQ4
This commit is contained in:
Nexoniarz
parent
438e7af141
commit
4ad49ed5f2
18 changed files with 1945 additions and 81 deletions
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@ -49,6 +49,14 @@
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#define R_RCR 0x44 // Rx config
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#define R_9346CR 0x50 // unlocks the config registers
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#define R_CONFIG1 0x52
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#define R_CONFIG2 0x53
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#define R_CONFIG3 0x54
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#define R_CONFIG5 0x56
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#define R_EEE_LED 0x1B
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#define R_EPHYAR 0x80 // the PCIe PHY's registers
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#define R_DLLPR 0xD0
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#define R_MISC1 0xF2
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#define R_INTRMIT 0xE2 // interrupt mitigation
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#define R_PHYAR 0x60 // the MII window
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#define R_PHYSTATUS 0x6C
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#define R_PMCH 0x6F // PLL power
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@ -107,6 +115,11 @@
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// MXDMA short. It would have worked and been slower, which is the worst kind
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// of wrong to leave in a register constant.
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#define RCR_UNLIMITED 0x0000E700
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// What Linux's rtl_init_rxcfg() writes on the 8168G and later instead:
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// 128-byte early interrupt, multiple descriptors per DMA, unlimited burst,
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// early receive off.
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#define RCR_GEN_G (0x8000 | 0x4000 | 0x0700 | 0x0800)
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#define TCR_AUTO_FIFO 0x00000080 // 8168E-VL and later: the chip sizes its FIFOs
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#define TCR_IFG_STD 0x03000000
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#define TCR_MXDMA 0x00000700
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@ -282,7 +295,21 @@ mac_ocp_write(struct r8169 *r, uint16 reg, uint16 val)
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wr32(r, R_MAC_OCP, OCP_FLAG | ((uint32)(reg >> 1) << 16) | val);
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}
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// The extended (ERI) registers, all four bytes at once.
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// The extended (ERI) registers. `mask` picks the bytes, bit 0 the lowest:
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// several of these registers share a word with ones that must not change.
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static void
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eri_write_mask(struct r8169 *r, int addr, int mask, uint32 val)
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{
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wr32(r, R_ERIDR, val);
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wr32(r, R_ERIAR, OCP_FLAG | ((uint32)mask << 12) | addr);
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for (int i = 0; i < 100; i++) {
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microdelay(10);
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if (!(rd32(r, R_ERIAR) & OCP_FLAG))
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return;
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}
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}
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// All four bytes at once.
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static uint32
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eri_read(struct r8169 *r, int addr)
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{
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@ -315,7 +342,7 @@ r8169_gen_g(uint32 xid)
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switch (xid) {
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case 0x4C0: case 0x4C1: case 0x5C8: case 0x509:
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case 0x500: case 0x501: case 0x502:
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case 0x540: case 0x541:
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case 0x540: case 0x541: case 0x6C0:
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return 1;
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}
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return 0;
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@ -347,6 +374,202 @@ r8169_takeover_g(struct r8169 *r)
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wait_ll_ready(r);
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}
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// --- the 8168H as Linux sets it up ------------------------------------------
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//
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// From Linux 6.18 drivers/net/ethernet/realtek/r8169_main.c
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// (rtl_hw_start_8168h_1, rtl_hw_aspm_clkreq_enable) and r8169_phy_config.c
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// (rtl8168h_2_hw_phy_config), GPL-2.0, carried over register for register.
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// Without them the chip runs on its power-on FIFO sizes and PHY tuning and
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// with ASPM as the firmware left it, and moves frames, slowly and with drops.
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// The one part left out is the PHY firmware patch (rtl_nic/rtl8168h-2.fw),
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// which needs the root filesystem this runs before.
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static void
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ephy_write(struct r8169 *r, int reg, uint16 val)
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{
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wr32(r, R_EPHYAR, 0x80000000u | ((uint32)(reg & 0x1F) << 16) | val);
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for (int i = 0; i < 100; i++) {
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microdelay(10);
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if (!(rd32(r, R_EPHYAR) & 0x80000000u))
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break;
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}
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microdelay(10);
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}
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static uint16
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ephy_read(struct r8169 *r, int reg)
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{
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wr32(r, R_EPHYAR, (uint32)(reg & 0x1F) << 16);
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for (int i = 0; i < 100; i++) {
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microdelay(10);
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uint32 v = rd32(r, R_EPHYAR);
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if (v & 0x80000000u)
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return (uint16)v;
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}
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return 0xFFFF;
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}
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static void
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mac_ocp_modify(struct r8169 *r, uint16 reg, uint16 clear, uint16 set)
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{
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mac_ocp_write(r, reg, (mac_ocp_read(r, reg) & ~clear) | set);
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}
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static int
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phy_read_paged(struct r8169 *r, int page, int reg)
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{
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mii_write(r, 0x1F, (uint16)page);
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int v = mii_read(r, reg);
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mii_write(r, 0x1F, 0);
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return v;
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}
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static void
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phy_write_paged(struct r8169 *r, int page, int reg, uint16 val)
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{
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mii_write(r, 0x1F, (uint16)page);
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mii_write(r, reg, val);
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mii_write(r, 0x1F, 0);
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}
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static void
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phy_modify_paged(struct r8169 *r, int page, int reg, uint16 clear, uint16 set)
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{
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mii_write(r, 0x1F, (uint16)page);
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int v = mii_read(r, reg);
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if (v >= 0)
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mii_write(r, reg, (uint16)((v & ~clear) | set));
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mii_write(r, 0x1F, 0);
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}
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static void
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phy_param(struct r8169 *r, uint16 parm, uint16 clear, uint16 set)
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{
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mii_write(r, 0x1F, 0x0A43);
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mii_write(r, 0x13, parm);
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int v = mii_read(r, 0x14);
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if (v >= 0)
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mii_write(r, 0x14, (uint16)((v & ~clear) | set));
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mii_write(r, 0x1F, 0);
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}
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// PCIe Link Control, low two bits: L0s and L1. Linux clears L1 on this chip
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// and on the bridge above it unless the vendor has marked it safe, for "random
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// device stop working problems as well as full system hangs". Firmware
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// leaves it on. A link that drops into L1 between frames costs a wake-up per
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// burst and on some boards stalls outright, which is a download that crawls.
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static void
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aspm_off(struct pci_dev *d)
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{
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uint8 cap = pci_find_cap(d, 0x10);
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if (cap) {
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uint32 v = pci_read32(d->bus, d->slot, d->func, cap + 0x10);
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pci_write32(d->bus, d->slot, d->func, cap + 0x10, v & ~3u);
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}
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}
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static void
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r8169_aspm_off(struct r8169 *r)
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{
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struct pci_dev *d = r->pdev;
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// The vendor's flag that ASPM is safe on this board (rtl_aspm_is_safe).
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if (mac_ocp_read(r, 0xC0B2) & 0xF)
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return;
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aspm_off(d);
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for (int i = 0; i < pci_count(); i++) {
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struct pci_dev *b = pci_get(i);
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if (b && (b->header_type & 0x7F) == 1 &&
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pci_read8(b->bus, b->slot, b->func, 0x19) == d->bus)
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aspm_off(b);
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}
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// And in the chip: no L1.2 trigger, no clock request, ASPM off.
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mac_ocp_modify(r, 0xE092, 0x00FF, 0);
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wr8(r, R_CONFIG2, rd8(r, R_CONFIG2) & ~0x80);
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wr8(r, R_CONFIG5, rd8(r, R_CONFIG5) & ~0x01);
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}
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// rtl_hw_start_8168h_1. Config registers must be unlocked.
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static void
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r8169_start_8168h(struct r8169 *r)
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{
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static const struct { uint8 reg; uint16 clear, set; } ephy[] = {
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{ 0x1E, 0x0800, 0x0001 },
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{ 0x1D, 0x0000, 0x0800 },
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{ 0x05, 0xFFFF, 0x2089 },
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{ 0x06, 0xFFFF, 0x5881 },
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{ 0x04, 0xFFFF, 0x854A },
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{ 0x01, 0xFFFF, 0x068B },
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};
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for (unsigned i = 0; i < sizeof ephy / sizeof ephy[0]; i++)
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ephy_write(r, ephy[i].reg,
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(ephy_read(r, ephy[i].reg) & ~ephy[i].clear) | ephy[i].set);
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eri_write(r, 0xC8, (0x08u << 16) | 0x02); // FIFO sizes
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eri_write(r, 0xE8, (0x10u << 16) | 0x06);
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eri_write_mask(r, 0xCC, 0x1, 0x38); // pause thresholds
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eri_write_mask(r, 0xD0, 0x1, 0x48);
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eri_write(r, 0xDC, eri_read(r, 0xDC) & ~1u); // reset the packet filter
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eri_write(r, 0xDC, eri_read(r, 0xDC) | 1u);
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eri_write(r, 0xDC, eri_read(r, 0xDC) | 0x1C);
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eri_write_mask(r, 0x5F0, 0x3, 0x4F87);
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wr32(r, R_MISC, rd32(r, R_MISC) & ~MISC_RXDV_GATE);
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eri_write_mask(r, 0xC0, 0x3, 0);
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eri_write_mask(r, 0xB8, 0x3, 0);
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wr8(r, R_EEE_LED, rd8(r, R_EEE_LED) & ~0x07); // rtl8168_config_eee_mac
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eri_write(r, 0x1B0, eri_read(r, 0x1B0) | 0x3);
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wr8(r, R_DLLPR, rd8(r, R_DLLPR) & ~0x40); // PFM off
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wr8(r, R_MISC1, rd8(r, R_MISC1) & ~0x40); // PFM in D3cold off
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wr8(r, R_DLLPR, rd8(r, R_DLLPR) & ~0x80); // 10M power saving off
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eri_write(r, 0x1B0, eri_read(r, 0x1B0) & ~(1u << 12));
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wr8(r, R_CONFIG3, rd8(r, R_CONFIG3) & ~0x02); // Rdy_to_L23 off
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int saw = phy_read_paged(r, 0x0C42, 0x13);
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if (saw > 0 && (saw & 0x3FFF) > 0)
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mac_ocp_modify(r, 0xD412, 0x0FFF, (16000000 / (saw & 0x3FFF)) & 0x0FFF);
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mac_ocp_modify(r, 0xE056, 0x00F0, 0x0000);
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mac_ocp_modify(r, 0xE052, 0x6000, 0x8008);
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mac_ocp_modify(r, 0xE0D6, 0x01FF, 0x017F);
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mac_ocp_modify(r, 0xD420, 0x0FFF, 0x047F);
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mac_ocp_write(r, 0xE63E, 0x0001);
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mac_ocp_write(r, 0xE63E, 0x0000);
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mac_ocp_write(r, 0xC094, 0x0000);
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mac_ocp_write(r, 0xC09E, 0x0000);
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}
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// rtl8168h_2_hw_phy_config, less the firmware patch.
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static void
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r8169_phy_8168h(struct r8169 *r)
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{
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phy_param(r, 0x808A, 0x003F, 0x000A); // CHIN EST parameter
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phy_param(r, 0x0811, 0x0000, 0x0800); // R-tune and PGA-retune on
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phy_modify_paged(r, 0x0A42, 0x16, 0x0000, 0x0002);
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phy_modify_paged(r, 0x0A44, 0x11, 0, 1u << 11); // gphy 10M
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// ADC bias offset, from the MAC's OCP space.
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mac_ocp_write(r, 0xDD02, 0x807D);
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uint16 d1 = mac_ocp_read(r, 0xDD02), d2 = mac_ocp_read(r, 0xDD00);
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uint16 ioffset = ((d2 >> 1) & 0x7FF8) | (d2 & 0x0007) | ((d1 & 0x80) ? 0x8000 : 0);
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if (ioffset != 0xFFFF)
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phy_write_paged(r, 0x0BCF, 0x16, ioffset);
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// TX low-pass corner.
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int data = phy_read_paged(r, 0x0BCD, 0x16);
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if (data >= 0) {
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uint16 rlen = (data & 0xF) > 3 ? (data & 0xF) - 3 : 0;
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phy_write_paged(r, 0x0BCD, 0x17, rlen | rlen << 4 | rlen << 8 | rlen << 12);
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}
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phy_modify_paged(r, 0x0A44, 0x11, 1u << 7, 0); // PHY PFM off
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phy_modify_paged(r, 0x0A43, 0x10, 1u << 0, 0); // 10M PLL off: off
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phy_modify_paged(r, 0x0A43, 0x10, 1u << 2, 0); // ALDPS off
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phy_modify_paged(r, 0x0A43, 0x11, 0, 1u << 4); // EEE
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}
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// The PHY up and negotiating: page 0, out of power-down, autoneg on and
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// restarted. Power-down is what firmware leaves set after a shutdown, and
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// the old code ORed autoneg into BMCR and kept it.
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@ -620,6 +843,10 @@ r8169_probe(struct pci_dev *d)
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if (xid == 0x540 || xid == 0x541)
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eri_write(r, 0x1A8, eri_read(r, 0x1A8) | 0xFC000000);
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wr32(r, R_MISC, rd32(r, R_MISC) & ~MISC_RXDV_GATE);
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if (xid == 0x541 || xid == 0x6C0) {
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r8169_aspm_off(r);
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r8169_start_8168h(r);
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}
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}
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// CPCR is deliberately left alone.
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@ -635,13 +862,16 @@ r8169_probe(struct pci_dev *d)
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// unlike the 8139 it has no other programming model to be in.
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wr16(r, R_RMS, BUFSZ);
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wr8(r, R_MTPS, 0x3B);
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// EarlySize on the 8168E-VL and later, TxPacketMax before, as in Linux.
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wr8(r, R_MTPS, r->gen_g ? 0x27 : 0x3B);
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wr16(r, R_INTRMIT, 0); // no interrupt coalescing
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wr64(r, R_RDSAR, r->rx_phys);
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wr64(r, R_TNPDS, r->tx_phys);
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wr32(r, R_TCR, TCR_IFG_STD | TCR_MXDMA);
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wr32(r, R_RCR, RCR_APM | RCR_AM | RCR_AB | RCR_UNLIMITED);
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wr32(r, R_TCR, TCR_IFG_STD | TCR_MXDMA | (r->gen_g ? TCR_AUTO_FIFO : 0));
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wr32(r, R_RCR, RCR_APM | RCR_AM | RCR_AB |
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(r->gen_g ? RCR_GEN_G : RCR_UNLIMITED));
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// Multicast: everything. The stack filters, and a hash filter that is wrong
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// drops IPv6 neighbour discovery in a way that looks like a routing problem.
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@ -651,6 +881,11 @@ r8169_probe(struct pci_dev *d)
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wr8(r, R_CR, CR_RE | CR_TE);
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wr8(r, R_9346CR, C9346_LOCK);
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{
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uint32 xid = (rd32(r, R_TCR) >> 20) & 0xFCF;
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if (xid == 0x541 || xid == 0x6C0)
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r8169_phy_8168h(r);
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}
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r8169_phy_up(r);
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wr16(r, R_ISR, 0xFFFF); // clear anything left over
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@ -33,7 +33,6 @@ extern const struct pci_driver xhci_driver;
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extern const struct pci_driver virtio_gpu_driver;
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extern const struct pci_driver e1000_driver;
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extern const struct pci_driver ac97_driver;
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extern const struct pci_driver r8169_driver;
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extern const struct pci_driver rtl8139_driver;
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extern const struct pci_driver ahci_driver;
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extern const struct pci_driver nvme_driver;
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@ -47,7 +46,9 @@ static const struct pci_driver *drivers[] = {
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&virtio_gpu_driver,
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&vga_pci_driver,
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&e1000_driver,
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&r8169_driver,
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// &r8169_driver -- the RTL8168 is driven by Linux's own r8169 through
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// LDLS (etc/schinit/ldls-r8169.job), which a kernel driver here would
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// claim first. The native driver stays in the tree as the fallback.
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&rtl8139_driver,
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&xhci_driver,
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&ahci_driver,
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Loading…
Reference in a new issue