Demand paging, the RTL8168H, links that come up late, and Ctrl+Alt+F1..F12
- Anonymous memory can be reserved without being backed: large mappings, MAP_NORESERVE and PROT_NONE are recorded and each page appears, zeroed, on first touch -- from trap() for the program, from uva2ka() for the kernel on its behalf. WebKit reserves 4 GB at start and touches a sliver; backing it all failed with ENOMEM and Epiphany aborted. - r8169: the 8168G generation and later (the laptop's 8168H, XID 541) are taken from the firmware's out-of-band mode, get their PLL powered, the receive gate opened, and their PHY reached through the OCP window. The PHY's power-down bit is cleared; the old code kept it while restarting autonegotiation. Untested on the hardware so far. - The network thread follows each device's link into lwIP. The link was read once at attach, 0.02 s into boot; real autonegotiation takes seconds, so on hardware the interface stayed down for good. - Twelve terminals, switched with Ctrl+Alt+F1..F12 by default: the keys X uses, so the console and the desktop agree. AltGr+F-key is gone from the defaults (chvt -c altgr+F brings it back). - SO_PASSCRED on Unix sockets, with SCM_CREDENTIALS delivered by recvmsg. WebKit sets it on its IPC sockets and aborted when refused. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01S1giNvrHTrPMPw7V6x1kQ4
This commit is contained in:
Nexoniarz
parent
3113eff7fe
commit
54b25708c3
24 changed files with 4166 additions and 68 deletions
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@ -51,6 +51,13 @@
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#define R_CONFIG1 0x52
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#define R_PHYAR 0x60 // the MII window
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#define R_PHYSTATUS 0x6C
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#define R_PMCH 0x6F // PLL power
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#define R_ERIDR 0x70 // extended register window: data
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#define R_ERIAR 0x74 // and address
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#define R_GPHY_OCP 0xB8 // the PHY's registers, 8168G and later
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#define R_MAC_OCP 0xB0 // the MAC's own OCP registers
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#define R_MCU 0xD3
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#define R_MISC 0xF0
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#define R_RMS 0xDA // largest frame the chip will accept
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#define R_CPCR 0xE0 // "C+" command
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#define R_RDSAR 0xE4 // Rx descriptors, 64-bit
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@ -77,6 +84,15 @@
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#define PHYSTATUS_LINK 0x02
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#define MCU_NOW_IS_OOB 0x80 // the firmware, not a driver, owns the MAC
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#define MCU_LL_READY 0x02 // link-list FIFO ready
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#define MISC_RXDV_GATE 0x00080000
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#define OCP_FLAG 0x80000000
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#define OCP_STD_PHY_BASE 0xA400
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#define BMCR_PDOWN 0x0800
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#define BMCR_ANENABLE 0x1000
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#define BMCR_ANRESTART 0x0200
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// Rx config: accept frames addressed to us, broadcast and multicast, with the
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// largest DMA burst and Rx FIFO threshold the chip offers. Promiscuous is
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// deliberately not set -- a NIC that hands the stack every frame on the wire
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@ -128,6 +144,8 @@ struct r8169 {
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int tx_next;
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uint8 mac[6];
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int ready;
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int gen_g; // 8168G or later: see r8169_gen_g()
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uint16 ocp_base; // the PHY page selected through register 0x1F
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uint64 rx_packets, tx_packets;
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struct spinlock lock;
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@ -168,7 +186,7 @@ wr64(struct r8169 *r, int o, uint64 v)
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#define PHYAR_FLAG 0x80000000
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static void
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mii_write(struct r8169 *r, int reg, uint16 val)
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phyar_write(struct r8169 *r, int reg, uint16 val)
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{
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wr32(r, R_PHYAR, PHYAR_FLAG | ((reg & 0x1F) << 16) | val);
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for (int i = 0; i < 1000; i++) {
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@ -179,7 +197,7 @@ mii_write(struct r8169 *r, int reg, uint16 val)
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}
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static int
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mii_read(struct r8169 *r, int reg)
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phyar_read(struct r8169 *r, int reg)
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{
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wr32(r, R_PHYAR, (reg & 0x1F) << 16);
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for (int i = 0; i < 1000; i++) {
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@ -191,6 +209,164 @@ mii_read(struct r8169 *r, int reg)
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return -1;
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}
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// From the 8168G on, the PHY sits behind an OCP window instead: its standard
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// registers are at 0xA400 + 2*reg, and "select page N" through register 0x1F
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// becomes a base address. PHYAR still answers reads on some of these chips,
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// which is how this driver got away without it -- until a write mattered.
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static void
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ocp_phy_write(struct r8169 *r, uint16 addr, uint16 val)
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{
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wr32(r, R_GPHY_OCP, OCP_FLAG | ((uint32)(addr >> 1) << 16) | val);
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for (int i = 0; i < 1000; i++) {
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microdelay(20);
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if (!(rd32(r, R_GPHY_OCP) & OCP_FLAG))
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return;
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}
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}
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static int
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ocp_phy_read(struct r8169 *r, uint16 addr)
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{
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wr32(r, R_GPHY_OCP, (uint32)(addr >> 1) << 16);
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for (int i = 0; i < 1000; i++) {
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microdelay(20);
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uint32 v = rd32(r, R_GPHY_OCP);
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if (v & OCP_FLAG)
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return (int)(v & 0xFFFF);
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}
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return -1;
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}
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static void
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mii_write(struct r8169 *r, int reg, uint16 val)
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{
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if (!r->gen_g) {
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phyar_write(r, reg, val);
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return;
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}
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if (reg == 0x1F) {
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r->ocp_base = val ? (uint16)(val << 4) : OCP_STD_PHY_BASE;
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return;
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}
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if (r->ocp_base != OCP_STD_PHY_BASE)
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reg -= 0x10;
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ocp_phy_write(r, (uint16)(r->ocp_base + reg * 2), val);
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}
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static int
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mii_read(struct r8169 *r, int reg)
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{
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if (!r->gen_g)
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return phyar_read(r, reg);
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if (r->ocp_base != OCP_STD_PHY_BASE)
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reg -= 0x10;
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return ocp_phy_read(r, (uint16)(r->ocp_base + reg * 2));
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}
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// The MAC's OCP registers. No completion flag to wait on.
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static uint16
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mac_ocp_read(struct r8169 *r, uint16 reg)
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{
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wr32(r, R_MAC_OCP, (uint32)(reg >> 1) << 16);
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return (uint16)rd32(r, R_MAC_OCP);
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}
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static void
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mac_ocp_write(struct r8169 *r, uint16 reg, uint16 val)
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{
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wr32(r, R_MAC_OCP, OCP_FLAG | ((uint32)(reg >> 1) << 16) | val);
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}
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// The extended (ERI) registers, all four bytes at once.
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static uint32
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eri_read(struct r8169 *r, int addr)
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{
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wr32(r, R_ERIAR, (0xFu << 12) | addr);
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for (int i = 0; i < 100; i++) {
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microdelay(10);
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if (rd32(r, R_ERIAR) & OCP_FLAG)
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return rd32(r, R_ERIDR);
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}
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return 0;
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}
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static void
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eri_write(struct r8169 *r, int addr, uint32 val)
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{
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wr32(r, R_ERIDR, val);
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wr32(r, R_ERIAR, OCP_FLAG | (0xFu << 12) | addr);
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for (int i = 0; i < 100; i++) {
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microdelay(10);
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if (!(rd32(r, R_ERIAR) & OCP_FLAG))
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return;
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}
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}
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// Which XIDs are the 8168G generation and later: 8168G, GU, 8411B, EP, H.
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// They share the OCP windows and the firmware handover below.
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static int
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r8169_gen_g(uint32 xid)
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{
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switch (xid) {
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case 0x4C0: case 0x4C1: case 0x5C8: case 0x509:
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case 0x500: case 0x501: case 0x502:
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case 0x540: case 0x541:
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return 1;
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}
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return 0;
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}
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static void
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wait_ll_ready(struct r8169 *r)
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{
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for (int i = 0; i < 42; i++) {
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if (rd8(r, R_MCU) & MCU_LL_READY)
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return;
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microdelay(100);
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}
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}
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// Taking the chip from the firmware. A laptop that was last running Windows,
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// or that keeps Wake-on-LAN armed, hands it over in out-of-band mode with the
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// receive path gated off: the MAC answers its registers and moves no frames.
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static void
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r8169_takeover_g(struct r8169 *r)
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{
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wr32(r, R_MISC, rd32(r, R_MISC) | MISC_RXDV_GATE);
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wr8(r, R_CR, rd8(r, R_CR) & ~(CR_TE | CR_RE));
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microdelay(1000);
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wr8(r, R_MCU, rd8(r, R_MCU) & ~MCU_NOW_IS_OOB);
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mac_ocp_write(r, 0xE8DE, mac_ocp_read(r, 0xE8DE) & ~(1u << 14));
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wait_ll_ready(r);
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mac_ocp_write(r, 0xE8DE, mac_ocp_read(r, 0xE8DE) | (1u << 15));
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wait_ll_ready(r);
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}
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// The PHY up and negotiating: page 0, out of power-down, autoneg on and
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// restarted. Power-down is what firmware leaves set after a shutdown, and
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// the old code ORed autoneg into BMCR and kept it.
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static void
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r8169_phy_up(struct r8169 *r)
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{
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mii_write(r, 0x1F, 0);
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int bmcr = mii_read(r, 0);
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if (bmcr < 0)
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return;
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bmcr &= ~BMCR_PDOWN;
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mii_write(r, 0, (uint16)bmcr);
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if (r->gen_g) {
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// Wait for the PHY to report it is on: its state, low three bits of
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// OCP 0xA420, reads 3 once it is.
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for (int i = 0; i < 100; i++) {
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int st = ocp_phy_read(r, 0xA420);
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if (st >= 0 && (st & 7) == 3)
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break;
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microdelay(1000);
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}
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}
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mii_write(r, 0, (uint16)(bmcr | BMCR_ANENABLE | BMCR_ANRESTART));
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}
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// --- the class ops ----------------------------------------------------------
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static const unsigned char *
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@ -392,6 +568,7 @@ r8169_probe(struct pci_dev *d)
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}
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r->pdev = d;
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r->ocp_base = OCP_STD_PHY_BASE;
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initlock(&r->lock, "r8169");
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pci_enable(d, PCI_CMD_MEMORY | PCI_CMD_BUS_MASTER);
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@ -404,6 +581,10 @@ r8169_probe(struct pci_dev *d)
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return -1;
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}
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r->gen_g = r8169_gen_g((rd32(r, R_TCR) >> 20) & 0xFCF);
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if (r->gen_g)
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r8169_takeover_g(r);
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// Soft reset, and wait for the chip to say it finished.
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wr8(r, R_CR, CR_RST);
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for (int i = 0; i < 1000; i++) {
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@ -426,6 +607,16 @@ r8169_probe(struct pci_dev *d)
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wr8(r, R_9346CR, C9346_UNLOCK); // config registers are writable now
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if (r->gen_g) {
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// The PLL powered, the extra ERI bits the 8168H wants with it, and the
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// receive gate opened again.
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wr8(r, R_PMCH, rd8(r, R_PMCH) | 0xC0);
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uint32 xid = (rd32(r, R_TCR) >> 20) & 0xFCF;
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if (xid == 0x540 || xid == 0x541)
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eri_write(r, 0x1A8, eri_read(r, 0x1A8) | 0xFC000000);
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wr32(r, R_MISC, rd32(r, R_MISC) & ~MISC_RXDV_GATE);
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}
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// CPCR is deliberately left alone.
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//
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// An earlier version set bit 3 here with a comment calling it "PCI multiple
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@ -455,14 +646,7 @@ r8169_probe(struct pci_dev *d)
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wr8(r, R_CR, CR_RE | CR_TE);
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wr8(r, R_9346CR, C9346_LOCK);
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// Restart autonegotiation. The PHY normally does this out of reset, and
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// asking again costs nothing and covers the case where firmware left it
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// parked -- BMCR bit 12 is autoneg enable, bit 9 restarts it.
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{
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int bmcr = mii_read(r, 0);
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if (bmcr >= 0)
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mii_write(r, 0, (uint16)(bmcr | 0x1200));
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}
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r8169_phy_up(r);
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wr16(r, R_ISR, 0xFFFF); // clear anything left over
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wr16(r, R_IMR, ISR_ROK | ISR_RER | ISR_TOK | ISR_TER |
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