acpi: uACPI, for interrupt routing, the power button and power-off
The firmware's AML is now interpreted. uACPI 6.1.1 (MIT) is fetched by ports/uacpi, checksum-verified, and compiled into the kernel unmodified, the same way lwIP is. kernel/acpi/host.c is its host layer: memory, mapping, port and PCI config I/O, time, mutexes and events that spin before the scheduler exists, the SCI, and an "acpi" thread for the work the SCI defers. PCI interrupts go where the board says. pci_init() now routes every device's INTx through the root bridge's _PRT before drivers bind. It follows link devices' _CRS, uses a bridge's own _PRT where the namespace has one, and swizzles through bridges that don't. Before this, INTx waited on the 8259's line number, which is the wrong pin in APIC mode. irq_register() takes a trigger mode rather than a level/low flag, because q35's links and most SCIs are level, active-high. The MADT's interrupt source overrides are now parsed, and are what places the SCI. The power button syncs the filesystems and powers off. shutdown() and reboot() go through the firmware's S5 and reset register first, and only then fall back to the emulators' ports, which a real board does not answer. Tested under QEMU: q35 with MSI off routes xHCI to GSI 22, level/active-high, and it takes real interrupts with nothing polled. system_powerdown powers off q35 and i440fx (QEMU exits 0), and q35 with 4 CPUs boots from NVMe with USB hot-plug working alongside. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01S1giNvrHTrPMPw7V6x1kQ4
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@ -68,6 +68,9 @@ struct pci_dev {
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uint16 vendor, device;
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uint8 class, subclass, prog_if, revision;
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uint8 irq; // interrupt line, 0xFF when unrouted
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// How that line is signalled, an IRQ_* mode from irq.h. PCI's level/low
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// unless ACPI's routing says otherwise -- see kernel/acpi/aml.c.
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uint8 irq_mode;
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uint8 header_type;
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struct pci_bar bar[6];
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const char *driver; // name of whatever claimed it, or 0
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