acpi: uACPI, for interrupt routing, the power button and power-off
The firmware's AML is now interpreted. uACPI 6.1.1 (MIT) is fetched by ports/uacpi, checksum-verified, and compiled into the kernel unmodified, the same way lwIP is. kernel/acpi/host.c is its host layer: memory, mapping, port and PCI config I/O, time, mutexes and events that spin before the scheduler exists, the SCI, and an "acpi" thread for the work the SCI defers. PCI interrupts go where the board says. pci_init() now routes every device's INTx through the root bridge's _PRT before drivers bind. It follows link devices' _CRS, uses a bridge's own _PRT where the namespace has one, and swizzles through bridges that don't. Before this, INTx waited on the 8259's line number, which is the wrong pin in APIC mode. irq_register() takes a trigger mode rather than a level/low flag, because q35's links and most SCIs are level, active-high. The MADT's interrupt source overrides are now parsed, and are what places the SCI. The power button syncs the filesystems and powers off. shutdown() and reboot() go through the firmware's S5 and reset register first, and only then fall back to the emulators' ports, which a real board does not answer. Tested under QEMU: q35 with MSI off routes xHCI to GSI 22, level/active-high, and it takes real interrupts with nothing polled. system_powerdown powers off q35 and i440fx (QEMU exits 0), and q35 with 4 CPUs boots from NVMe with USB hot-plug working alongside. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01S1giNvrHTrPMPw7V6x1kQ4
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Nexoniarz
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16 changed files with 1237 additions and 14 deletions
334
kernel/acpi/aml.c
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334
kernel/acpi/aml.c
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// SPDX-License-Identifier: GPL-2.0-or-later
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//
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// What the kernel uses AML for. See include/acpi.h.
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//
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// Interrupt routing is the reason this exists. A PCI device's config space
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// names an interrupt line, but that number is the 8259's: the firmware
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// programmed it for an OS running the legacy PICs, and with the I/O APIC in
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// use the device is on some other pin entirely. Which pin is written down
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// only in the namespace, as each PCI root bridge's _PRT -- a table from
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// (device, INTx pin) to either a GSI or a "link device" whose _CRS holds the
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// GSI. Without reading it, every INTx device on a real board waited on the
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// wrong pin, and only MSI and the poller (kernel/dev/irq.c) kept anything
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// working at all.
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//
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// The rest is what every machine expects of an OS once it has ACPI: the
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// power button powers it off cleanly, and power-off and reset go through the
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// firmware's own registers rather than an emulator's magic ports.
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#include "types.h"
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#include "defs.h"
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#include "param.h"
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#include "x86.h"
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#include "spinlock.h"
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#include "pci.h"
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#include "irq.h"
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#include "acpi.h"
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#include <uacpi/uacpi.h>
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#include <uacpi/utilities.h>
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#include <uacpi/namespace.h>
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#include <uacpi/resources.h>
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#include <uacpi/event.h>
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#include <uacpi/sleep.h>
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static int ready;
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static uacpi_interrupt_ret power_button(uacpi_handle ctx);
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void
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acpi_aml_init(void)
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{
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uacpi_status st;
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if (acpi_rsdp_phys() == 0)
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return;
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st = uacpi_initialize(0);
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if (uacpi_unlikely_error(st)) {
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cprintf("acpi: tables not usable: %s\n", uacpi_status_to_string(st));
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return;
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}
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st = uacpi_namespace_load();
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if (uacpi_unlikely_error(st)) {
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cprintf("acpi: AML would not load: %s\n", uacpi_status_to_string(st));
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return;
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}
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// \_PIC(1): tell the firmware the I/O APIC is in use, so that _PRT answers
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// with I/O APIC inputs rather than PIC lines. Before _INI runs, which on
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// some boards reads the answer.
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uacpi_set_interrupt_model(UACPI_INTERRUPT_MODEL_IOAPIC);
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st = uacpi_namespace_initialize();
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if (uacpi_unlikely_error(st)) {
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cprintf("acpi: namespace would not initialize: %s\n",
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uacpi_status_to_string(st));
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return;
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}
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st = uacpi_install_fixed_event_handler(UACPI_FIXED_EVENT_POWER_BUTTON,
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power_button, 0);
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if (uacpi_unlikely_error(st) && st != UACPI_STATUS_COMPILED_OUT)
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kinfo("acpi: no fixed power button: %s\n", uacpi_status_to_string(st));
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uacpi_finalize_gpe_initialization();
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ready = 1;
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kinfo("acpi: namespace loaded\n");
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}
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// --- power -------------------------------------------------------------------
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// Run in the worker thread, not the SCI handler: syncing the filesystems
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// sleeps, and S5 runs AML.
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static void
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power_off_work(uacpi_handle ctx)
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{
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(void)ctx;
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cprintf("acpi: power button pressed; syncing and powering off\n");
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schfs_ksync_all();
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acpi_poweroff();
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cprintf("acpi: power-off failed; it is safe to switch off now\n");
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}
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static uacpi_interrupt_ret
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power_button(uacpi_handle ctx)
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{
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static int once;
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(void)ctx;
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if (!once) {
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once = 1;
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uacpi_kernel_schedule_work(UACPI_WORK_NOTIFICATION, power_off_work, 0);
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}
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return UACPI_INTERRUPT_HANDLED;
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}
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int
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acpi_poweroff(void)
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{
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if (!ready)
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return -1;
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if (uacpi_unlikely_error(uacpi_prepare_for_sleep_state(UACPI_SLEEP_STATE_S5)))
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return -1;
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cli();
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uacpi_enter_sleep_state(UACPI_SLEEP_STATE_S5);
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sti();
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return -1;
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}
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int
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acpi_reboot(void)
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{
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if (!ready)
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return -1;
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uacpi_reboot();
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return -1;
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}
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// --- PCI interrupt routing ---------------------------------------------------
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#define MAXBUS 256
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// The bridge leading to each secondary bus, from the devices pci_init found.
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static struct pci_dev *upstream[MAXBUS];
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static uacpi_namespace_node *root_bridge;
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static uacpi_iteration_decision
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found_root(void *user, uacpi_namespace_node *node, uacpi_u32 depth)
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{
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uacpi_u64 bbn = 0;
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(void)user;
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(void)depth;
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// _BBN is the bridge's first bus. Absent means 0, and bus 0 is the one
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// whose devices are all that most machines have.
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uacpi_eval_simple_integer(node, "_BBN", &bbn);
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if (bbn == 0 && root_bridge == 0) {
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root_bridge = node;
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return UACPI_ITERATION_DECISION_BREAK;
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}
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return UACPI_ITERATION_DECISION_CONTINUE;
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}
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// The namespace node of the device at (slot, func) below `parent`: the child
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// whose _ADR says so.
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static uacpi_namespace_node *
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child_at(uacpi_namespace_node *parent, int slot, int func)
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{
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uacpi_namespace_node *child = 0;
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uacpi_u64 adr;
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while (uacpi_namespace_node_next(parent, &child) == UACPI_STATUS_OK) {
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if (uacpi_eval_simple_integer(child, "_ADR", &adr) == UACPI_STATUS_OK &&
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adr == (((uacpi_u64)slot << 16) | (uacpi_u64)func))
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return child;
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}
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return 0;
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}
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struct irqfind {
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uint32 index;
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int gsi;
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int mode;
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};
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static int
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mode_of(int triggering, int polarity)
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{
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int level = triggering == UACPI_TRIGGERING_LEVEL;
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int low = polarity == UACPI_POLARITY_ACTIVE_LOW;
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return level ? (low ? IRQ_LEVEL_LOW : IRQ_LEVEL_HIGH)
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: (low ? IRQ_EDGE_LOW : IRQ_EDGE_HIGH);
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}
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static uacpi_iteration_decision
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link_irq(void *user, uacpi_resource *r)
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{
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struct irqfind *f = user;
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if (r->type == UACPI_RESOURCE_TYPE_IRQ && r->irq.num_irqs > 0) {
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f->gsi = r->irq.irqs[f->index < r->irq.num_irqs ? f->index : 0];
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f->mode = mode_of(r->irq.triggering, r->irq.polarity);
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return UACPI_ITERATION_DECISION_BREAK;
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}
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if (r->type == UACPI_RESOURCE_TYPE_EXTENDED_IRQ &&
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r->extended_irq.num_irqs > 0) {
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f->gsi = r->extended_irq.irqs[f->index < r->extended_irq.num_irqs
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? f->index : 0];
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f->mode = mode_of(r->extended_irq.triggering, r->extended_irq.polarity);
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return UACPI_ITERATION_DECISION_BREAK;
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}
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return UACPI_ITERATION_DECISION_CONTINUE;
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}
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// Look (slot, pin) up in a _PRT. Returns the GSI, or -1. A link device's
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// current setting is used as it stands: firmware programs every link at
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// boot, and one it left disabled is reported rather than reconfigured.
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static int
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prt_lookup(uacpi_pci_routing_table *t, int slot, int pin, int *mode)
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{
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for (uacpi_size i = 0; i < t->num_entries; i++) {
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uacpi_pci_routing_table_entry *e = &t->entries[i];
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if ((e->address >> 16) != (uint32)slot || e->pin != pin)
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continue;
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if (e->source == 0) {
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*mode = IRQ_LEVEL_LOW; // a bare GSI is PCI's signalling
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return e->index;
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}
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uacpi_resources *res;
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struct irqfind f = { e->index, -1, IRQ_LEVEL_LOW };
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if (uacpi_get_current_resources(e->source, &res) != UACPI_STATUS_OK)
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return -1;
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uacpi_for_each_resource(res, link_irq, &f);
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uacpi_free_resources(res);
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if (f.gsi <= 0) {
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uacpi_object_name nm = uacpi_namespace_node_name(e->source);
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char name[5] = { nm.text[0], nm.text[1], nm.text[2], nm.text[3], 0 };
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cprintf("acpi: link %s for slot %d is disabled\n", name, slot);
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return -1;
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}
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*mode = f.mode;
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return f.gsi;
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}
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return -1;
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}
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static int
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route_one(struct pci_dev *d, uacpi_pci_routing_table *roottab, int *mode)
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{
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// The chain of bridges from bus 0 down to this device's bus.
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struct pci_dev *chain[8];
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int n = 0, bus = d->bus;
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while (bus != 0 && n < 8 && upstream[bus]) {
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chain[n++] = upstream[bus];
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bus = upstream[bus]->bus;
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}
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if (bus != 0)
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return -1; // a bus not reached from bus 0
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// Walk down the namespace alongside it, as far as the namespace describes
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// the bridges. The deepest bridge with its own _PRT is where the lookup
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// happens; below it, INTx pins are swizzled by the PCI-to-PCI bridge rule.
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uacpi_namespace_node *node = root_bridge;
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uacpi_pci_routing_table *tab = roottab, *owned = 0;
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int at = n; // chain[at..] lies below tab's bus
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for (int i = n - 1; i >= 0 && node; i--) {
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node = child_at(node, chain[i]->slot, chain[i]->func);
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uacpi_pci_routing_table *t;
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if (node && uacpi_get_pci_routing_table(node, &t) == UACPI_STATUS_OK) {
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if (owned)
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uacpi_free_pci_routing_table(owned);
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tab = owned = t;
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at = i;
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}
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}
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int pin = pci_read8(d->bus, d->slot, d->func, 0x3D) - 1; // 0 = INTA
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int slot = d->slot;
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for (int i = 0; i < at; i++) {
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pin = (pin + slot) % 4;
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slot = chain[i]->slot;
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}
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// The device is now (slot, pin) on the bus `tab` describes: that bridge's
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// secondary bus, or bus 0 for the root table.
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int gsi = prt_lookup(tab, slot, pin, mode);
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if (owned)
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uacpi_free_pci_routing_table(owned);
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return gsi;
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}
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void
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acpi_pci_route(void)
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{
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uacpi_pci_routing_table *roottab;
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int i, routed = 0;
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if (!ready)
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return;
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uacpi_find_devices("PNP0A08", found_root, 0); // PCI Express
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if (!root_bridge)
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uacpi_find_devices("PNP0A03", found_root, 0); // conventional PCI
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if (!root_bridge ||
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uacpi_get_pci_routing_table(root_bridge, &roottab) != UACPI_STATUS_OK) {
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kinfo("acpi: no _PRT on the root bridge; PCI lines left as found\n");
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return;
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}
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for (i = 0; i < pci_count(); i++) {
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struct pci_dev *d = pci_get(i);
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if ((d->header_type & 0x7F) == 1) {
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int sec = pci_read8(d->bus, d->slot, d->func, 0x19);
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if (sec > 0 && sec < MAXBUS)
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upstream[sec] = d;
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}
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}
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for (i = 0; i < pci_count(); i++) {
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struct pci_dev *d = pci_get(i);
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int mode, gsi;
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if (pci_read8(d->bus, d->slot, d->func, 0x3D) == 0)
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continue; // uses no INTx pin at all
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gsi = route_one(d, roottab, &mode);
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if (gsi < 0)
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continue;
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if (gsi >= NIRQ_IOAPIC) {
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// A second I/O APIC's input. Not reachable here; MSI still is.
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d->irq = 0xFF;
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continue;
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}
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if (gsi != d->irq)
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kinfo("acpi: %d:%d.%d INT%c is gsi %d, not %d\n", d->bus, d->slot,
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d->func, 'A' + pci_read8(d->bus, d->slot, d->func, 0x3D) - 1,
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gsi, d->irq);
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d->irq = gsi;
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d->irq_mode = mode;
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routed++;
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}
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uacpi_free_pci_routing_table(roottab);
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kinfo("acpi: %d PCI interrupt%s routed through _PRT\n", routed,
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routed == 1 ? "" : "s");
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}
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