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acpi: uACPI, for interrupt routing, the power button and power-off

Browse source 
The firmware's AML is now interpreted. uACPI 6.1.1 (MIT) is fetched by
ports/uacpi, checksum-verified, and compiled into the kernel unmodified,
the same way lwIP is. kernel/acpi/host.c is its host layer: memory,
mapping, port and PCI config I/O, time, mutexes and events that spin
before the scheduler exists, the SCI, and an "acpi" thread for the
work the SCI defers.

PCI interrupts go where the board says. pci_init() now routes every
device's INTx through the root bridge's _PRT before drivers bind. It
follows link devices' _CRS, uses a bridge's own _PRT where the namespace
has one, and swizzles through bridges that don't. Before this, INTx
waited on the 8259's line number, which is the wrong pin in APIC mode.
irq_register() takes a trigger mode rather than a level/low flag,
because q35's links and most SCIs are level, active-high. The MADT's
interrupt source overrides are now parsed, and are what places the SCI.

The power button syncs the filesystems and powers off. shutdown() and
reboot() go through the firmware's S5 and reset register first, and
only then fall back to the emulators' ports, which a real board does
not answer.

Tested under QEMU: q35 with MSI off routes xHCI to GSI 22,
level/active-high, and it takes real interrupts with nothing polled.
system_powerdown powers off q35 and i440fx (QEMU exits 0), and q35
with 4 CPUs boots from NVMe with USB hot-plug working alongside.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01S1giNvrHTrPMPw7V6x1kQ4
This commit is contained in:
Nexoniarz 2026-10-22 16:12:28 +02:00
commit 93f981c7ea
16 changed files with 1237 additions and 14 deletions
Download patch file Download diff file Expand all files Collapse all files

62
kernel/arch/x86_64/acpi.c
View file

@ -24,6 +24,8 @@
#include "mmu.h"
#include "proc.h"
#include "x86.h"
#include "irq.h"
#include "acpi.h"
extern struct cpu cpus[NCPU];
extern int ncpu;
@ -79,6 +81,7 @@ struct acpi_madt {
// routing overrides that ioapic.c does not consult yet.
#define MADT_LAPIC 0
#define MADT_IOAPIC 1
#define MADT_ISO 2
#define MADT_LAPIC_OVERRIDE 5
#define MADT_X2APIC 9
@ -123,6 +126,25 @@ struct madt_lapic_override {
uint64 addr;
} __attribute__((packed));
// Interrupt source override: ISA IRQ `source` is really GSI `gsi`, signalled
// as `flags` says -- polarity in bits 1:0, trigger in 3:2, each 0 for "as the
// bus does it", 1 for high/edge and 3 for low/level.
struct madt_iso {
struct madt_entry e;
uint8 bus;
uint8 source;
uint32 gsi;
uint16 flags;
} __attribute__((packed));
static struct {
int set;
uint32 gsi;
uint16 flags;
} iso[16];
static uint64 rsdp_phys;
static int
checksum_ok(const void *p, uint32 len)
{
@ -267,6 +289,7 @@ acpi_init(void)
struct acpi_rsdp *rsdp = find_rsdp();
if (!rsdp)
return 0;
rsdp_phys = V2P(rsdp);
// The FADT first, for the PM timer: PM_TMR_BLK at offset 76, and bit 8 of
// the flags at 112 says whether it counts 32 bits or 24. A hardware-reduced
@ -326,6 +349,15 @@ acpi_init(void)
}
break;
}
case MADT_ISO: {
struct madt_iso *o = (struct madt_iso *)p;
if (o->source < 16) {
iso[o->source].set = 1;
iso[o->source].gsi = o->gsi;
iso[o->source].flags = o->flags;
}
break;
}
case MADT_LAPIC_OVERRIDE: {
struct madt_lapic_override *o = (struct madt_lapic_override *)p;
lapic = (uint *)P2V(o->addr);
@ -351,3 +383,33 @@ acpi_init(void)
ncpu, ncpu == 1 ? "" : "s", lapic, ioapicid);
return 1;
}
uint64
acpi_rsdp_phys(void)
{
return rsdp_phys;
}
int
acpi_isa_gsi(int isa, int dflt, int *mode)
{
int level, low;
*mode = dflt;
if (isa < 0 || isa >= 16 || !iso[isa].set)
return isa;
level = IRQ_IS_LEVEL(dflt);
low = dflt == IRQ_LEVEL_LOW || dflt == IRQ_EDGE_LOW;
switch (iso[isa].flags & 3) {
case 1: low = 0; break;
case 3: low = 1; break;
}
switch ((iso[isa].flags >> 2) & 3) {
case 1: level = 0; break;
case 3: level = 1; break;
}
*mode = level ? (low ? IRQ_LEVEL_LOW : IRQ_LEVEL_HIGH)
: (low ? IRQ_EDGE_LOW : IRQ_EDGE_HIGH);
return iso[isa].gsi;
}

8
kernel/arch/x86_64/ioapic.c
View file

@ -88,8 +88,12 @@ ioapicroute(int irq, int cpunum, int level_low)
{
uint lo = T_IRQ0 + irq;
if(level_low)
lo |= INT_LEVEL | INT_ACTIVELOW;
// A mode from include/irq.h; 1, the PCI case, is what `level_low` meant
// when it was a flag.
if(level_low == 1 || level_low == 2)
lo |= INT_LEVEL;
if(level_low == 1 || level_low == 3)
lo |= INT_ACTIVELOW;
// Program the destination before unmasking, so the entry is never briefly
// live pointing at CPU 0 when it was meant for another.