kernel: the clock ran 7x slow because the GPU never acknowledged its interrupt
fastfetch reported 3 seconds of uptime after 15 real ones, `time` claimed
3.12s for a 20-second command, and ping's one-second interval was closer to
six. One cause, not three: `ticks` was advancing at ~14.5 Hz instead of 100.
It was not the timer. virtio-gpu-pci shares IRQ 11 with the e1000 and
registered no interrupt handler at all. PCI INTx is level-triggered, so the
device held the line asserted, the kernel signalled EOI, and it fired again
immediately -- 72,000 interrupts a second, 83% of CPU0, starving the tick.
The e1000's handler read ICR as zero half a million times, correctly
answering "not mine", which is what made it look like a network-free problem.
Reading virtio's ISR byte clears it and drops the line. That is the fix.
irq_dispatch now measures each line's rate against the TSC -- not ticks,
which is the first casualty of a storm -- and names the attached handlers
once above 20000/s. It reproduces the original fault as a single line.
Found along the way, and fixed because they were real:
- lapicinit loaded TICR with xv6's uncalibrated 10000000, whose own comment
admitted it was never measured. calibrate_timers() now measures the LAPIC
and the TSC against the 8254 PIT. (It came back at 999.9 MHz, so this was
not the bug -- but the next machine is not obliged to be 1 GHz.)
- microdelay() was an empty function body. Every microdelay(1000) in the
xHCI reset path and the USB hub power-on sequence returned instantly.
- HZ is a constant in param.h now, not the literal 100 written out at a
dozen ticks-to-seconds conversions. USER_HZ is separate and deliberately
does not follow it: musl answers sysconf(_SC_CLK_TCK) with 100 always, so
times() and /proc/stat scale at the syscall boundary the way Linux does.
- TIOCGWINSZ answered a hardcoded 24x80. gfx_cols()/gfx_rows() have known
the real geometry all along; at 1024x768 the console is 128x48, so every
program that lays out a screen was formatting for the wrong one.
- TCFLSH fell through to the catch-all `return 0`, claiming to discard
input without discarding any.
uptime now advances 5.01 seconds per 5 real seconds. schfs-check passes.
Full investigation, including the two wrong hypotheses and the measurement
flaw that protected them, in docs/history/kernel.md section 13.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01VQ7Qx8E1q1M1bbCq8QLHS2
This commit is contained in:
Nexoniarz
parent
c874811679
commit
9d4cdb44fc
17 changed files with 479 additions and 37 deletions
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@ -49,6 +49,85 @@ lapicw(int index, int value)
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lapic[ID]; // wait for write to finish, by reading
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}
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// ---------------------------------------------------------------------
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// Timer calibration
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// ---------------------------------------------------------------------
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// The LAPIC timer counts down at the APIC bus frequency, and nothing in the
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// architecture tells you what that frequency is. xv6 loaded TICR with
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// 10000000 and hoped; its own comment admitted the gap -- "if xv6 cared more
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// about precise timekeeping, TICR would be calibrated using an external time
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// source." That value yields the intended 100 Hz only if the bus happens to
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// run at exactly 1 GHz.
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//
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// Under KVM it does not, and the error is not subtle. The kernel believed
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// ticks arrived 100 times a second while they were arriving roughly 18 times
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// a second, so every number derived from ticks was wrong by that same factor,
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// in the same direction, everywhere at once: uptime ran slow, `time` reported
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// three seconds for twenty, ping's one-second interval stretched to six. It
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// read as three unrelated bugs in three unrelated programs. It was this line.
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//
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// So measure it. The 8254 PIT is exactly the external time source the comment
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// asked for: its input clock is fixed at 1193182 Hz by the hardware, it is
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// always present, and channel 2 is the one whose gate software can raise and
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// whose output software can poll -- a stopwatch that needs no interrupt, which
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// matters because this runs before the IDT is ready to take one.
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#define PIT_HZ 1193182 // 8254 input clock, fixed by definition
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#define PIT_CH2 0x42
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#define PIT_CMD 0x43
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#define PIT_GATE 0x61 // bit 0: ch2 gate, bit 1: speaker, bit 5: ch2 output
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uint lapic_timer_hz; // measured LAPIC timer counts per second
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uint64 tsc_hz; // measured TSC cycles per second
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static void
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calibrate_timers(void)
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{
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// 50 ms: long enough that the port I/O around the measurement is noise,
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// short enough that nobody notices it in boot time. The count fits in the
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// 16 bits the PIT has (59659), which is the real upper bound here.
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const uint us = 50000;
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uint count = (uint)(((uint64)PIT_HZ * us) / 1000000);
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// Channel 2, mode 0 (interrupt on terminal count), lobyte then hibyte.
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// Gate high so it counts; the speaker bit stays clear so the box is silent.
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outb(PIT_GATE, (inb(PIT_GATE) & ~0x02) | 0x01);
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outb(PIT_CMD, 0xB0);
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outb(PIT_CH2, count & 0xFF);
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outb(PIT_CH2, (count >> 8) & 0xFF);
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// A free-running LAPIC counter for the duration: one-shot, masked, started
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// at the largest count there is so it cannot wrap inside 50 ms.
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lapicw(TDCR, X1);
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lapicw(TIMER, MASKED);
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lapicw(TICR, 0xFFFFFFFF);
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uint64 tsc0 = rdtsc();
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uint lap0 = lapic[TCCR];
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while (!(inb(PIT_GATE) & 0x20)) // ch2 output rises at terminal count
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;
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uint lap1 = lapic[TCCR];
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uint64 tsc1 = rdtsc();
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lapicw(TICR, 0); // stop counting
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// TCCR counts down, so elapsed counts are start minus end.
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lapic_timer_hz = (uint)(((uint64)(lap0 - lap1) * 1000000) / us);
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tsc_hz = ((tsc1 - tsc0) * 1000000) / us;
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// If the measurement came back implausible -- no LAPIC, a hypervisor that
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// stops the counter, a PIT that never raises its output -- fall back to the
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// old assumption rather than dividing by zero and taking the machine down.
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// Wrong-but-running beats a triple fault, and the printed value says which
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// case this is.
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if (lapic_timer_hz < HZ * 1000u) {
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cprintf("cpu0: lapic calibration implausible (%u Hz), assuming 1 GHz bus\n",
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lapic_timer_hz);
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lapic_timer_hz = 1000000000u; // the 1 GHz that TICR=10000000 implied
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}
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}
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void
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lapicinit(void)
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{
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@ -58,13 +137,19 @@ lapicinit(void)
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// Enable local APIC; set spurious interrupt vector.
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lapicw(SVR, ENABLE | (T_IRQ0 + IRQ_SPURIOUS));
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// The timer repeatedly counts down at bus frequency
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// from lapic[TICR] and then issues an interrupt.
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// If xv6 cared more about precise timekeeping,
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// TICR would be calibrated using an external time source.
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// The timer counts down at the APIC bus frequency and interrupts at zero.
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// What that frequency *is*, calibrate_timers() had to go and measure --
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// see the comment above it for why loading a constant here does not work.
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if (lapic_timer_hz == 0) {
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calibrate_timers();
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cprintf("cpu0: lapic timer %u Hz, tsc %u MHz, tick = %u counts at %d Hz\n",
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lapic_timer_hz, (uint)(tsc_hz / 1000000),
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lapic_timer_hz / HZ, HZ);
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}
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lapicw(TDCR, X1);
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lapicw(TIMER, PERIODIC | (T_IRQ0 + IRQ_TIMER));
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lapicw(TICR, 10000000);
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lapicw(TICR, lapic_timer_hz / HZ);
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// Disable logical interrupt lines.
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lapicw(LINT0, MASKED);
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@ -132,10 +217,36 @@ lapiceoi(void)
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}
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// Spin for a given number of microseconds.
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// On real hardware would want to tune this dynamically.
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//
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// This was an empty function body -- xv6's stub, carrying a comment saying
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// real hardware would want to tune it dynamically. Nothing ever did, so every
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// microdelay() in the tree returned immediately: the xHCI reset sequence, the
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// USB hub power-on wait, the UART drain. Those delays are written into the
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// specifications because the hardware genuinely needs the time, and a port
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// that "works anyway" is one that is racing and winning.
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//
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// The TSC is the right clock for this: calibrate_timers() measured it in the
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// same pass as the LAPIC, and unlike the LAPIC timer it is not already busy
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// driving the tick.
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void
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microdelay(int us)
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{
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if (us <= 0)
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return;
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// Before calibration (early boot, and the AP trampoline) there is no
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// measured frequency to work from. Spin on a rough count instead: the
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// figure is wrong, but being approximately late is the entire point of the
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// call, and being instantly early is what broke it.
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if (tsc_hz == 0) {
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for (volatile int i = 0; i < us * 100; i++)
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;
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return;
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}
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uint64 end = rdtsc() + ((uint64)us * tsc_hz) / 1000000;
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while (rdtsc() < end)
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asm volatile("pause");
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}
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#define CMOS_PORT 0x70
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