audio: /dev/dsp, AudioEngine, and an AC'97 under it
A program that wants to make a sound opens /dev/dsp, writes PCM, and closes
it. That is what UNIX audio has always been and it now exists here:
tone 440 2
Three pieces, in the order a sample passes through them. **/dev/dsp** is a
character device where write() is audio and a handful of OSS ioctls say what
the samples are. **AudioEngine** is everything above a driver that is not
specific to a chip -- the format, whether there is room, and what a write does
when there is not. **A driver** is bound by class, exactly as a display driver
is: device_find_class(DEVCLASS_AUDIO).
OSS numbering rather than something new, because every UNIX audio program ever
written already knows it and the only thing a different set would achieve is
making ports harder. They are read/write ioctls, which is the part that
matters: a program asks for 44100, the device sets 48000 and writes 48000
back, the program resamples. One that ignores the answer plays 9% fast, and
that is its bug rather than the driver's.
**The engine is deliberately one stream.** Mixing several programs is a real
feature with a real design behind it, and building it before anything had
played a single sound would be exactly what docs/plan/1.0.md keeps a register
for: work that exists and is connected to nothing. The second program that
wants to play at the same time is what should cause it to be written.
**audio_wait() sleeps on the timer tick, not on the device.** That looks like
the lazy choice and is not: a ring that drains is a ring with room, so asking
again in ten milliseconds always makes progress, whereas sleeping on the card
makes audio depend on an interrupt arriving. On a machine whose line is
misrouted that is not a stutter, it is a writer that never wakes. The handler
still accounts for finished buffers -- deleting it would cost efficiency, not
correctness -- and it retires descriptors through the same `tail` pointer
queue() uses, so the two cannot disagree about what is in flight.
**AC'97 first because HDA is two unproven things at once.** It is the simplest
audio device that exists on real machines and in QEMU both. Intel HDA is what
the laptop actually has and is a much larger driver; writing it against an
interface nothing had ever played through would have meant debugging the
driver and the interface simultaneously. HDA arrives as a second
struct audio_ops and nothing above it changes -- which is the entire point of
the class.
Two things the wiring needed: PCI class 0x04 now maps to DEVCLASS_AUDIO (the
driver bound and /proc/devices showed it, but audio_get() found nothing,
because the class byte had never been translated), and include/x86.h grew
inw() -- AC'97's mixer is all 16-bit registers and reading one a byte at a
time returns the low half twice on some codecs.
**Tested by measuring what came out, not by not crashing.** QEMU's wav backend
writes the guest's audio to a file; `tone 440 2` produced 1.97 seconds of
44.1 kHz stereo with peak amplitude 14177 against the generator's table
maximum of 14178, and 880 zero crossings per second -- 440 Hz exactly. wav is
on every QEMU target rather than a host backend, because a build machine may
have no sound card and it is the only backend whose output can be checked.
Both supported configurations: one boot each, no traps, no panics, socktest
and memfdtest green.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
This commit is contained in:
Nexoniarz
parent
3eb2e97f7b
commit
9fea18b18b
18 changed files with 1110 additions and 5 deletions
413
kernel/drivers/audio/ac97.c
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413
kernel/drivers/audio/ac97.c
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// AC'97, the audio class's first driver.
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//
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// Written from the Intel 82801 datasheet's audio chapter. It is the simplest
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// PC audio device that exists on real machines and in QEMU both, which is why
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// it is first: the point of this driver is to prove the class and /dev/dsp
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// with the least chip-specific code possible. Intel HDA -- which is what a
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// laptop built this century actually has -- is a much larger driver, and
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// writing it against an interface nothing had ever played a sound through
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// would be writing two unproven things at once.
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//
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// Two register files, both **I/O ports** rather than MMIO:
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//
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// NAM BAR0, the mixer. Volume, and the codec's own capabilities.
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// NABM BAR1, bus mastering. The descriptor list, and the DMA engine that
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// walks it.
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//
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// The DMA engine reads a *buffer descriptor list*: 32 entries, each naming a
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// physical address and a length in samples. It plays entry CIV, and stops when
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// it reaches LVI -- the "last valid index". Playing continuously is therefore
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// not a matter of starting it and walking away; it is a matter of keeping LVI
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// ahead of CIV, which is what queue() does.
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#include "types.h"
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#include "defs.h"
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#include "param.h"
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#include "x86.h"
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#include "spinlock.h"
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#include "sleeplock.h"
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#include "fs.h"
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#include "file.h"
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#include "memlayout.h"
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#include "mmu.h"
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#include "pci.h"
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#include "device.h"
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#include "audio.h"
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#include "dma.h"
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#include "irq.h"
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// --- NAM, the mixer ---------------------------------------------------------
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#define NAM_RESET 0x00
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#define NAM_MASTER_VOL 0x02
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#define NAM_PCM_OUT_VOL 0x18
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#define NAM_EXT_ID 0x28
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#define NAM_EXT_CTRL 0x2A
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#define NAM_PCM_FRONT_RATE 0x2C
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#define EXT_VRA 0x0001 // variable rate: the codec can do 44100
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// --- NABM, the bus master ---------------------------------------------------
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//
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// The PCM *out* box starts at 0x10. There are three boxes (in, out, mic) and
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// they have the same shape, which is why the offsets below are written as a
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// base plus a field rather than as constants.
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#define PO_BASE 0x10
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#define PO_BDBAR (PO_BASE + 0x00) // uint32: physical address of the list
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#define PO_CIV (PO_BASE + 0x04) // uint8: entry being played now
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#define PO_LVI (PO_BASE + 0x05) // uint8: last entry the engine may play
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#define PO_SR (PO_BASE + 0x06) // uint16: status
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#define PO_PICB (PO_BASE + 0x08) // uint16: samples left in this entry
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#define PO_CR (PO_BASE + 0x0B) // uint8: control
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#define CR_RPBM 0x01 // run
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#define CR_RR 0x02 // reset the box
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#define CR_IOCE 0x10 // interrupt on completion
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#define SR_DCH 0x01 // DMA halted
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#define SR_BCIS 0x08 // buffer completion interrupt
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#define SR_LVBCI 0x04 // last valid buffer played
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#define GLOB_CTRL 0x2C
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#define GLOB_STA 0x30
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// --- the ring ---------------------------------------------------------------
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//
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// 32 descriptors of 4 KB each: 128 KB, which at 48 kHz stereo is about
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// two thirds of a second. Long enough that a writer can fall behind for a
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// scheduling quantum without a gap, short enough that stopping is prompt.
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#define NDESC 32
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#define DESC_BYTES 4096
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struct bdl_entry {
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uint32 addr;
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uint16 samples; // *samples*, not bytes: 16-bit words, so bytes/2
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uint16 flags;
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};
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#define BDL_IOC 0x8000 // interrupt when this one finishes
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struct ac97 {
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uint16 nam, nabm; // I/O port bases
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struct bdl_entry *bdl; // NDESC entries, DMA memory
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uint8 *buf; // NDESC * DESC_BYTES, DMA memory
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uint32 bdl_phys, buf_phys;
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int head; // next descriptor to fill
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int tail; // oldest one still queued
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int filled[NDESC]; // bytes in each, 0 when free
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int running;
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struct spinlock lock;
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struct pci_dev *pdev;
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};
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static struct ac97 ac97dev;
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static struct ac97 *
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of(struct device *d)
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{
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(void)d;
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return ac97dev.nabm ? &ac97dev : 0;
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}
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// --- mixer ------------------------------------------------------------------
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// Volume is attenuation: 0 is loudest, and the mute bit is 0x8000. Writing 0
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// rather than a "sensible" level on purpose -- the kernel has no business
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// deciding how loud a machine is, and a device that comes up silent reads as
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// broken to whoever is testing it.
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static void
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mixer_init(struct ac97 *a)
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{
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outw(a->nam + NAM_RESET, 0);
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outw(a->nam + NAM_MASTER_VOL, 0x0000);
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outw(a->nam + NAM_PCM_OUT_VOL, 0x0000);
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}
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// --- the class ops ----------------------------------------------------------
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static int
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ac97_configure(struct device *d, struct audio_format *f)
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{
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struct ac97 *a = of(d);
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uint16 ext;
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if (!a)
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return -1;
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// Two channels always. AC'97 plays stereo; a mono stream would have to be
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// doubled, and doing that in the driver would hide it from the caller that
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// asked -- which is what the write-back in the ioctl is for.
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f->channels = 2;
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f->bits = AUDIO_FMT_S16LE;
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ext = inw(a->nam + NAM_EXT_ID);
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if (ext & EXT_VRA) {
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outw(a->nam + NAM_EXT_CTRL, inw(a->nam + NAM_EXT_CTRL) | EXT_VRA);
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outw(a->nam + NAM_PCM_FRONT_RATE, (uint16)f->rate);
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// What the codec settled on, which is not always what was asked: it is
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// entitled to round to something it can generate.
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f->rate = inw(a->nam + NAM_PCM_FRONT_RATE);
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} else {
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// No variable rate. 48 kHz is the only thing this codec plays, and saying
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// so is more useful than accepting 44100 and playing it 9% fast.
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f->rate = 48000;
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}
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return 0;
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}
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// How many descriptors the engine has finished with.
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// Descriptors with nothing in them, counted forward from where the next write
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// would go. Stops at the first one still holding audio, which is what makes
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// this the number of bytes a write can take without waiting.
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static int
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free_descs(struct ac97 *a)
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{
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int n = 0;
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for (int i = 0; i < NDESC; i++) {
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if (a->filled[(a->head + i) % NDESC])
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break;
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n++;
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}
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return n;
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}
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static int
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ac97_space(struct device *d)
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{
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struct ac97 *a = of(d);
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int n;
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if (!a)
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return 0;
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acquire(&a->lock);
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n = free_descs(a) * DESC_BYTES;
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release(&a->lock);
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return n;
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}
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static int
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ac97_queue(struct device *d, const void *pcm, int bytes)
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{
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struct ac97 *a = of(d);
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int civ, idx, take;
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if (!a)
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return -1;
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acquire(&a->lock);
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civ = inb(a->nabm + PO_CIV) % NDESC;
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idx = a->head;
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// Retire what the engine has finished with.
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//
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// `tail` is the oldest descriptor we still believe is queued; CIV is the one
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// being played. Everything between them is done. Doing this here as well as
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// in the interrupt handler is deliberate -- the handler is an optimisation,
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// and audio that only works when its interrupt arrives is audio that stops
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// dead on a machine whose line is misrouted.
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while (a->tail != civ && a->filled[a->tail]) {
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a->filled[a->tail] = 0;
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a->tail = (a->tail + 1) % NDESC;
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}
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if (a->filled[idx]) {
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release(&a->lock);
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return 0; // ring full
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}
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take = bytes > DESC_BYTES ? DESC_BYTES : bytes;
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memmove(a->buf + (uint64)idx * DESC_BYTES, pcm, take);
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a->bdl[idx].addr = a->buf_phys + (uint32)idx * DESC_BYTES;
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a->bdl[idx].samples = (uint16)(take / 2); // 16-bit words
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a->bdl[idx].flags = BDL_IOC;
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a->filled[idx] = take;
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a->head = (idx + 1) % NDESC;
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// LVI is the last entry the engine may play. Keeping it at the descriptor
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// just written is what makes this a queue rather than a one-shot.
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outb(a->nabm + PO_LVI, (uint8)idx);
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release(&a->lock);
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return take;
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}
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static void
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ac97_start(struct device *d)
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{
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struct ac97 *a = of(d);
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if (!a)
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return;
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acquire(&a->lock);
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if (!a->running) {
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outb(a->nabm + PO_CR, CR_RPBM | CR_IOCE);
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a->running = 1;
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}
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release(&a->lock);
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}
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static void
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ac97_stop(struct device *d)
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{
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struct ac97 *a = of(d);
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if (!a)
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return;
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acquire(&a->lock);
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outb(a->nabm + PO_CR, 0);
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outb(a->nabm + PO_CR, CR_RR); // reset the box: CIV, LVI, PICB to 0
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for (int i = 0; i < NDESC; i++)
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a->filled[i] = 0;
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a->head = 0;
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a->tail = 0;
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a->running = 0;
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release(&a->lock);
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}
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static int
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ac97_pending(struct device *d)
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{
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struct ac97 *a = of(d);
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int n = 0;
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if (!a)
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return 0;
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acquire(&a->lock);
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if (a->running && !(inw(a->nabm + PO_SR) & SR_DCH)) {
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for (int i = 0; i < NDESC; i++)
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if (a->filled[i])
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n += a->filled[i];
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}
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release(&a->lock);
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return n;
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}
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static const struct audio_ops ac97_ops = {
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.configure = ac97_configure,
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.space = ac97_space,
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.queue = ac97_queue,
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.start = ac97_start,
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.stop = ac97_stop,
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.pending = ac97_pending,
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};
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// --- interrupt --------------------------------------------------------------
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static void
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ac97_intr(void *arg)
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{
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struct ac97 *a = arg;
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uint16 sr;
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if (!a || !a->nabm)
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return;
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sr = inw(a->nabm + PO_SR);
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// Acknowledge by writing the bits back. A status bit left set on a
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// level-triggered line is an interrupt that re-fires for ever -- the same
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// shape as the e1000 bug in docs/history/kernel.md section 13.
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if (sr & (SR_BCIS | SR_LVBCI | SR_DCH))
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outw(a->nabm + PO_SR, sr & (SR_BCIS | SR_LVBCI | SR_DCH));
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{
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int civ = inb(a->nabm + PO_CIV) % NDESC;
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// Everything the engine has passed is free again. Through `tail` rather
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// than by clearing one entry, so this and ac97_queue() cannot disagree
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// about which descriptors are in flight.
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while (a->tail != civ && a->filled[a->tail]) {
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a->filled[a->tail] = 0;
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a->tail = (a->tail + 1) % NDESC;
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}
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}
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// The writer is asleep on the tick rather than on this device, so there is
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// nothing to wake -- see audio_wait(). Keeping the handler to "acknowledge
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// and account" is deliberate: an interrupt handler that can be deleted
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// without the audio stopping is one that cannot deadlock the audio either.
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}
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// --- probe ------------------------------------------------------------------
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static int
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ac97_probe(struct pci_dev *d)
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{
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struct ac97 *a = &ac97dev;
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if (a->nabm)
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return -1; // one is enough
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// Both BARs are I/O ports on this device, which is why nothing here maps
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// anything: `is_io` is what says so, and a driver that ioremapped these
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// would be mapping a port number as if it were an address.
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if (!d->bar[0].is_io || !d->bar[1].is_io ||
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!d->bar[0].base || !d->bar[1].base) {
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cprintf("ac97: expected two I/O BARs; not driving this device\n");
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return -1;
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}
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a->nam = (uint16)d->bar[0].base;
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a->nabm = (uint16)d->bar[1].base;
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a->pdev = d;
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initlock(&a->lock, "ac97");
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pci_enable(d, PCI_CMD_IO | PCI_CMD_BUS_MASTER);
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// The descriptor list and the audio itself, both from the DMA arena: the
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// engine reads them by physical address, and kalloc's pages are adjacent
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// only by chance.
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a->bdl = dma_alloc(NDESC * sizeof(struct bdl_entry), 4096);
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a->buf = dma_alloc(NDESC * DESC_BYTES, 4096);
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if (!a->bdl || !a->buf) {
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cprintf("ac97: no DMA memory for a %d KB ring\n",
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(NDESC * DESC_BYTES) / 1024);
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a->nabm = 0;
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return -1;
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}
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a->bdl_phys = (uint32)dma_phys(a->bdl);
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a->buf_phys = (uint32)dma_phys(a->buf);
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memset(a->bdl, 0, NDESC * sizeof(struct bdl_entry));
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memset(a->buf, 0, NDESC * DESC_BYTES);
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// Cold reset of the whole controller, then the PCM-out box.
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outl(a->nabm + GLOB_CTRL, 0x00000002);
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mixer_init(a);
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outb(a->nabm + PO_CR, CR_RR);
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for (int spin = 0; spin < 100000 && (inb(a->nabm + PO_CR) & CR_RR); spin++)
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;
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outl(a->nabm + PO_BDBAR, a->bdl_phys);
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if (d->irq != 0xFF && d->irq < 24)
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irq_register(d->irq, ac97_intr, a, "ac97", 1);
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kinfo("ac97: nam %x nabm %x, %d KB ring, irq %d\n",
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a->nam, a->nabm, (NDESC * DESC_BYTES) / 1024, d->irq);
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return 0;
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}
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static const struct pci_match ac97_match[] = {
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{ 0x8086, 0x2415, 0, 0 }, // 82801AA, which is what QEMU's -device AC97 is
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{ 0x8086, 0x2425, 0, 0 }, // 82801AB
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{ 0x8086, 0x2445, 0, 0 }, // 82801BA
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{ 0x8086, 0x24C5, 0, 0 }, // ICH4
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{ 0x8086, 0x24D5, 0, 0 }, // ICH5
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{ 0x8086, 0x266E, 0, 0 }, // ICH6
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{ 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
const struct pci_driver ac97_driver = {
|
||||
.name = "ac97",
|
||||
.devname = "audio",
|
||||
.match = ac97_match,
|
||||
.ops = &ac97_ops,
|
||||
.probe = ac97_probe,
|
||||
};
|
||||
|
|
@ -32,6 +32,7 @@ extern const struct pci_driver vga_pci_driver;
|
|||
extern const struct pci_driver xhci_driver;
|
||||
extern const struct pci_driver virtio_gpu_driver;
|
||||
extern const struct pci_driver e1000_driver;
|
||||
extern const struct pci_driver ac97_driver;
|
||||
|
||||
// Order matters here in one respect: virtio-gpu is offered the bus before the
|
||||
// VBE framebuffer driver, so that on a machine with both, the device with real
|
||||
|
|
@ -43,6 +44,7 @@ static const struct pci_driver *drivers[] = {
|
|||
&vga_pci_driver,
|
||||
&e1000_driver,
|
||||
&xhci_driver,
|
||||
&ac97_driver,
|
||||
};
|
||||
|
||||
void
|
||||
|
|
|
|||
Loading…
Reference in a new issue