include: one folder per subsystem, and includes that name it
Sixty-five headers sat side by side in include/, so `#include "irq.h"` said nothing about where irq.h was or what it belonged to, and errno.h, stat.h and fcntl.h at the top shadowed the system's for any host tool built with -I./include. They are in folders now -- arch/ core/ fs/ dev/ gfx/ net/ uapi/ (and ldls/ for the Linux driver layer) -- and every include names the folder, as Linux's do: "core/proc.h". Done mechanically and checked the hard way: the kernel built from this tree disassembles identically to the one built from the tree before it. The full image boots, and userland is the same set of programs. Paths in docs and comments follow; docs/guides/layout.md has a table of what is where, and tools/fix-includes.py rewrites old-style includes from the folders in the tree, for code written before this. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01S1giNvrHTrPMPw7V6x1kQ4
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Nexoniarz
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267 changed files with 1560 additions and 1440 deletions
255
include/arch/x86.h
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255
include/arch/x86.h
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#pragma once
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struct dtr {
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ushort limit;
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uint64 base;
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} __attribute__((packed));
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static inline uchar
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inb(ushort port)
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{
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uchar data;
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asm volatile("in %1,%0" : "=a" (data) : "d" (port));
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return data;
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}
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// Cycle counter. Not a clock -- it does not convert to time without knowing the
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// frequency, and it is not synchronised across cores -- but for "which of these
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// two paths costs more" it is exactly the right instrument, and the only one
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// with fine enough resolution to see inside a single syscall.
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static inline uint64
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rdtsc(void)
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{
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uint lo, hi;
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asm volatile("rdtsc" : "=a" (lo), "=d" (hi));
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return ((uint64)hi << 32) | lo;
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}
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// The x87/MMX/SSE register file, to and from a 512-byte, 16-byte-aligned area.
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static inline void
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fxsave(void *area)
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{
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asm volatile("fxsave64 (%0)" : : "r"(area) : "memory");
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}
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static inline void
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fxrstor(const void *area)
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{
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asm volatile("fxrstor64 (%0)" : : "r"(area) : "memory");
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}
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static inline void
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insl(int port, void *addr, int cnt)
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{
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asm volatile("cld; rep insl" :
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"=D" (addr), "=c" (cnt) :
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"d" (port), "0" (addr), "1" (cnt) :
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"memory", "cc");
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}
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static inline void
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outb(ushort port, uchar data)
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{
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asm volatile("out %0,%1" : : "a" (data), "d" (port));
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}
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// 16 bits. Added for AC'97, whose mixer is entirely 16-bit registers: reading
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// one of them a byte at a time returns the low half twice on some codecs,
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// because the read of the low byte is what latches the pair.
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static inline ushort
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inw(ushort port)
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{
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ushort data;
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asm volatile("inw %1,%0" : "=a" (data) : "d" (port));
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return data;
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}
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static inline uint
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inl(ushort port)
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{
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uint data;
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asm volatile("inl %1,%0" : "=a" (data) : "d" (port));
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return data;
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}
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static inline void
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outw(ushort port, ushort data)
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{
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asm volatile("out %0,%1" : : "a" (data), "d" (port));
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}
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// PCI configuration space is reached through a pair of 32-bit ports, so this
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// is not optional decoration -- see kernel/dev/pci.c.
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static inline void
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outl(ushort port, uint data)
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{
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asm volatile("outl %0,%1" : : "a" (data), "d" (port));
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}
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static inline void
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outsl(int port, const void *addr, int cnt)
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{
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asm volatile("cld; rep outsl" :
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"=S" (addr), "=c" (cnt) :
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"d" (port), "0" (addr), "1" (cnt) :
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"cc");
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}
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static inline void
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stosb(void *addr, int data, int cnt)
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{
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asm volatile("cld; rep stosb" :
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"=D" (addr), "=c" (cnt) :
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"0" (addr), "1" (cnt), "a" (data) :
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"memory", "cc");
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}
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// 64-bit-only helpers. `rep stosq` and `xchgq` do not exist in 32-bit mode, so
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// these must not even be parsed by the -m32 bootloader build -- they compiled
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// there before only because uint64 was accidentally 32 bits wide, which is the
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// bug include/core/types.h now asserts against.
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#ifdef __x86_64__
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static inline void
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stosq(void *addr, uint64 data, int cnt)
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{
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asm volatile("cld; rep stosq" :
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"=D" (addr), "=c" (cnt) :
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"0" (addr), "1" (cnt), "a" (data) :
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"memory", "cc");
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}
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struct segdesc;
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static inline void
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lgdt(struct segdesc *p, int size)
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{
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struct dtr d;
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d.limit = size - 1;
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d.base = (uint64)p;
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asm volatile("lgdt (%0)" : : "r" (&d));
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}
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struct gatedesc;
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static inline void
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lidt(struct gatedesc *p, int size)
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{
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struct dtr d;
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d.limit = size - 1;
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d.base = (uint64)p;
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asm volatile("lidt (%0)" : : "r" (&d));
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}
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static inline void
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ltr(ushort sel)
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{
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asm volatile("ltr %0" : : "r" (sel));
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}
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static inline uint64
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readeflags(void)
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{
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uint64 flags;
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asm volatile("pushfq; pop %0" : "=r" (flags));
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return flags;
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}
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static inline void
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cli(void)
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{
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asm volatile("cli");
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}
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static inline void
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sti(void)
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{
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asm volatile("sti");
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}
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static inline void
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hlt(void)
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{
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asm volatile("hlt");
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}
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static inline uint64
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xchg(volatile uint64 *addr, uint64 newval)
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{
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uint64 result;
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asm volatile("lock; xchgq %0, %1" :
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"+m" (*addr), "=a" (result) :
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"1" (newval) :
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"cc");
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return result;
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}
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#endif /* __x86_64__ */
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static inline uint64
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rcr2(void)
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{
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uint64 val;
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asm volatile("mov %%cr2,%0" : "=r" (val));
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return val;
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}
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static inline void
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lcr3(uint64 val)
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{
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asm volatile("mov %0,%%cr3" : : "r" (val));
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}
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// Invalidate the TLB entry for one page. Needed any time a PTE is changed
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// or cleared for an address space that may still be the active CR3 —
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// otherwise the CPU can keep translating through the stale entry until the
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// next full CR3 reload (context switch), silently reading/writing the
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// wrong physical page.
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static inline void
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invlpg(void *va)
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{
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asm volatile("invlpg (%0)" : : "r" (va) : "memory");
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}
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static inline void
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wrmsr(uint32 msr, uint64 val)
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{
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uint32 low = (uint32)val;
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uint32 high = (uint32)(val >> 32);
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asm volatile("wrmsr" : : "c" (msr), "a" (low), "d" (high));
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}
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static inline uint64
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rdmsr(uint32 msr)
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{
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uint32 low, high;
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asm volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
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return ((uint64)high << 32) | low;
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}
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static inline uint64
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readcs(void)
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{
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uint64 val;
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asm volatile("mov %%cs, %0" : "=r" (val));
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return val;
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}
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// CPUID. `leaf` in EAX, results in EAX/EBX/ECX/EDX.
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//
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// %rbx is callee-saved *and* the PIC base register on some builds, so it is
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// exchanged out rather than named as an operand -- naming it directly is the
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// classic way to get "inline asm clobbers reserved register" or, worse, silent
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// corruption in the caller.
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static inline void
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cpuid_leaf(uint32 leaf, uint32 *a, uint32 *b, uint32 *c, uint32 *d)
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{
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uint32 ra, rb, rc, rd;
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asm volatile("xchgq %%rbx, %q1\n\t"
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"cpuid\n\t"
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"xchgq %%rbx, %q1"
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: "=a"(ra), "=&r"(rb), "=c"(rc), "=d"(rd)
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: "0"(leaf), "2"(0));
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if (a) *a = ra;
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if (b) *b = rb;
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if (c) *c = rc;
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if (d) *d = rd;
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}
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