include: one folder per subsystem, and includes that name it

Sixty-five headers sat side by side in include/, so `#include "irq.h"`
said nothing about where irq.h was or what it belonged to, and errno.h,
stat.h and fcntl.h at the top shadowed the system's for any host tool
built with -I./include. They are in folders now -- arch/ core/ fs/
dev/ gfx/ net/ uapi/ (and ldls/ for the Linux driver layer) -- and
every include names the folder, as Linux's do: "core/proc.h".

Done mechanically and checked the hard way: the kernel built from this
tree disassembles identically to the one built from the tree before
it. The full image boots, and userland is the same set of programs.
Paths in docs and comments follow; docs/guides/layout.md has a table
of what is where, and tools/fix-includes.py rewrites old-style
includes from the folders in the tree, for code written before this.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01S1giNvrHTrPMPw7V6x1kQ4

kernel/arch/x86_64/acpi.c

@@ -16,17 +16,17 @@
 // Written from the ACPI specification. No table layout here is copied from
 // another kernel; they are all in chapter 5 of the published standard.
 
-#include "types.h"
-#include "hwinfo.h"
-#include "defs.h"
-#include "schboot.h"   // SCHBOOT_RSDP_ADDR: the loader/kernel hand-off
-#include "param.h"
-#include "memlayout.h"
-#include "mmu.h"
-#include "proc.h"
-#include "x86.h"
-#include "irq.h"
-#include "acpi.h"
+#include "core/types.h"
+#include "core/hwinfo.h"
+#include "core/defs.h"
+#include "arch/schboot.h"   // SCHBOOT_RSDP_ADDR: the loader/kernel hand-off
+#include "core/param.h"
+#include "arch/memlayout.h"
+#include "arch/mmu.h"
+#include "core/proc.h"
+#include "arch/x86.h"
+#include "core/irq.h"
+#include "dev/acpi.h"
 
 extern struct cpu cpus[NCPU];
 extern int ncpu;

kernel/arch/x86_64/e820.c

@@ -12,12 +12,12 @@
 // use -- and leaves the result in low memory. stage2main.c already parses it to
 // print detected RAM on the splash. The kernel simply never read it.
 
-#include "types.h"
-#include "defs.h"
-#include "memlayout.h"
-#include "mmu.h"
-#include "dma.h"   // DMA_ARENA_BYTES: the top of PHYSTOP must be able to hold it
-#include "hwinfo.h"
+#include "core/types.h"
+#include "core/defs.h"
+#include "arch/memlayout.h"
+#include "arch/mmu.h"
+#include "core/dma.h"   // DMA_ARENA_BYTES: the top of PHYSTOP must be able to hold it
+#include "core/hwinfo.h"
 
 // Set before kinit1() and never again. Starts at the old constant so that a
 // crash between entry and e820_init() behaves the way it always did rather
@@ -29,13 +29,13 @@ uint64 phystop = PHYSTOP_FALLBACK;
 // map and all a 32-bit device can reach.
 uint64 lowtop = PHYSTOP_FALLBACK;
 
-#include "schboot.h"   /* the hand-off block */
+#include "arch/schboot.h"   /* the hand-off block */
 
 #define E820_USABLE     1
 #define E820_MAXENTRIES SCHBOOT_E820_MAX
 
 // Every usable region, page aligned inwards and clipped to PHYSTOP_MAX.
-// kinit1() frees these; see include/memlayout.h for why a list and not just a
+// kinit1() frees these; see include/arch/memlayout.h for why a list and not just a
 // top address.
 struct memregion mem_usable[MEMREGION_MAX];
 int nmem_usable;

kernel/arch/x86_64/entry.S

@@ -26,8 +26,8 @@
 
 #define mboot_magic 0x1badb002
 #define mboot_flags 0x00010000
-#include "mmu.h"
-#include "schboot.h"
+#include "arch/mmu.h"
+#include "arch/schboot.h"
 
 /* A second entry point, for firmware that has already put us in long mode.
  *

kernel/arch/x86_64/entryother.S

@@ -1,6 +1,6 @@
-#include "asm.h"
-#include "memlayout.h"
-#include "mmu.h"
+#include "arch/asm.h"
+#include "arch/memlayout.h"
+#include "arch/mmu.h"
 
 # Each non-boot CPU ("AP") is started up in response to a STARTUP
 # IPI from the boot CPU.  Section B.4.2 of the Multi-Processor

kernel/arch/x86_64/ioapic.c

@@ -2,14 +2,14 @@
 // http://www.intel.com/design/chipsets/datashts/29056601.pdf
 // See also picirq.c.
 
-#include "types.h"
-#include "defs.h"
-#include "traps.h"
-#include "memlayout.h"
-#include "mmu.h"
-#include "mp.h"
-#include "param.h"
-#include "proc.h"
+#include "core/types.h"
+#include "core/defs.h"
+#include "arch/traps.h"
+#include "arch/memlayout.h"
+#include "arch/mmu.h"
+#include "arch/mp.h"
+#include "core/param.h"
+#include "core/proc.h"
 
 
 #define REG_ID     0x00  // Register index: ID
@@ -88,7 +88,7 @@ ioapicroute(int irq, int cpunum, int level_low)
 {
   uint lo = T_IRQ0 + irq;
 
-  // A mode from include/irq.h; 1, the PCI case, is what `level_low` meant
+  // A mode from include/core/irq.h; 1, the PCI case, is what `level_low` meant
   // when it was a flag.
   if(level_low == 1 || level_low == 2)
     lo |= INT_LEVEL;

kernel/arch/x86_64/ioperm.c

@@ -1,11 +1,11 @@
-// The TSS I/O permission bitmap. See include/ioperm.h for why.
+// The TSS I/O permission bitmap. See include/arch/ioperm.h for why.
 
-#include "types.h"
-#include "defs.h"
-#include "param.h"
-#include "mmu.h"
-#include "proc.h"
-#include "ioperm.h"
+#include "core/types.h"
+#include "core/defs.h"
+#include "core/param.h"
+#include "arch/mmu.h"
+#include "core/proc.h"
+#include "arch/ioperm.h"
 
 // The 64-bit TSS, written out rather than indexed.
 //

kernel/arch/x86_64/lapic.c

@@ -1,15 +1,15 @@
 // The local APIC manages internal (non-I/O) interrupts.
 // See Chapter 8 & Appendix C of Intel processor manual volume 3.
 
-#include "param.h"
-#include "types.h"
-#include "defs.h"
-#include "date.h"
-#include "memlayout.h"
-#include "traps.h"
-#include "mmu.h"
-#include "x86.h"
-#include "proc.h"  // ncpu
+#include "core/param.h"
+#include "core/types.h"
+#include "core/defs.h"
+#include "core/date.h"
+#include "arch/memlayout.h"
+#include "arch/traps.h"
+#include "arch/mmu.h"
+#include "arch/x86.h"
+#include "core/proc.h"  // ncpu
 
 // Local APIC registers, divided by 4 for use as uint[] indices.
 #define ID      (0x0020/4)   // ID

kernel/arch/x86_64/mp.c

@@ -2,14 +2,14 @@
 // Search memory for MP description structures.
 // http://developer.intel.com/design/pentium/datashts/24201606.pdf
 
-#include "types.h"
-#include "defs.h"
-#include "param.h"
-#include "memlayout.h"
-#include "mp.h"
-#include "x86.h"
-#include "mmu.h"
-#include "proc.h"
+#include "core/types.h"
+#include "core/defs.h"
+#include "core/param.h"
+#include "arch/memlayout.h"
+#include "arch/mp.h"
+#include "arch/x86.h"
+#include "arch/mmu.h"
+#include "core/proc.h"
 
 struct cpu cpus[NCPU];
 // Processors the firmware says exist.

kernel/arch/x86_64/trap.c

@@ -1,14 +1,14 @@
-#include "types.h"
-#include "defs.h"
-#include "irq.h"
-#include "param.h"
-#include "memlayout.h"
-#include "mmu.h"
-#include "proc.h"
-#include "x86.h"
-#include "traps.h"
-#include "spinlock.h"
-#include "posix.h"
+#include "core/types.h"
+#include "core/defs.h"
+#include "core/irq.h"
+#include "core/param.h"
+#include "arch/memlayout.h"
+#include "arch/mmu.h"
+#include "core/proc.h"
+#include "arch/x86.h"
+#include "arch/traps.h"
+#include "core/spinlock.h"
+#include "uapi/posix.h"
 
 uint *idt;
 extern addr_t vectors[];
@@ -139,7 +139,7 @@ trap(struct trapframe *tf)
     // interrupts used to be listed here one case at a time, which cannot work
     // for anything found on the PCI bus: a driver does not know its line
     // until it reads the device's config space at probe time, so there is no
-    // constant to write a case label for. See include/irq.h.
+    // constant to write a case label for. See include/core/irq.h.
     if(tf->trapno >= T_IRQ0 && tf->trapno < T_IRQ0 + NIRQ){
       irq_dispatch(tf->trapno - T_IRQ0);
       lapiceoi();

kernel/arch/x86_64/trapasm.S

@@ -9,7 +9,7 @@
 #       on EXIT to user (sysretq or iretq), write proc->fs_base to MSR.
 #
 # proc->fs_base is at byte offset 0x18 (24) inside struct proc.
-# proc pointer is at %gs:24 (PERCPU_PROC in include/proc.h); cpu is at %gs:16.
+# proc pointer is at %gs:24 (PERCPU_PROC in include/core/proc.h); cpu is at %gs:16.
 
 # -----------------------------------------------------------------------
 # Helper macro: write kernel_fs_base to IA32_FS_BASE.
@@ -49,9 +49,9 @@
 # Clobbers %rax, %rcx, %rdx. Caller must save them if needed.
 # -----------------------------------------------------------------------
 .macro WRITE_USER_FS
-    # proc, from the per-CPU block at %gs:24 (PERCPU_PROC in include/proc.h).
+    # proc, from the per-CPU block at %gs:24 (PERCPU_PROC in include/core/proc.h).
     # This used to be %fs:(-8), the __thread slot, which no longer exists --
-    # see the comment in include/proc.h for why those stopped being __thread.
+    # see the comment in include/core/proc.h for why those stopped being __thread.
     movq    %gs:24, %rax         # proc pointer
     movq    0x18(%rax), %rax     # proc->fs_base  (offset 24 = 0x18)
     movq    %rax, %rdx

kernel/arch/x86_64/vm.c

@@ -1,13 +1,13 @@
-#include "param.h"
-#include "types.h"
-#include "defs.h"
-#include "gfx.h"
-#include "x86.h"
-#include "memlayout.h"
-#include "mmu.h"
-#include "proc.h"
-#include "ioperm.h"
-#include "vmap.h"
+#include "core/param.h"
+#include "core/types.h"
+#include "core/defs.h"
+#include "gfx/gfx.h"
+#include "arch/x86.h"
+#include "arch/memlayout.h"
+#include "arch/mmu.h"
+#include "core/proc.h"
+#include "arch/ioperm.h"
+#include "arch/vmap.h"
 
 int mappages(pml4e_t *pgdir, void *va, addr_t size, addr_t pa, int perm);
 static pte_t * walkpgdir(pml4e_t *pml4, const void *va, int alloc);
@@ -15,7 +15,7 @@ static pte_t * walkpgdir(pml4e_t *pml4, const void *va, int alloc);
 
 // `cpu` and `proc` are no longer __thread variables; they live at fixed offsets
 // in the per-CPU block and are read through %gs at each use. See the long
-// comment in include/proc.h for why -- the short version is that __thread means
+// comment in include/core/proc.h for why -- the short version is that __thread means
 // per *thread*, the compiler caches the thread pointer across calls on that
 // basis, and a kernel thread changes CPU at every sched().
 
@@ -113,7 +113,7 @@ seginit(void)
   gdt = (struct segdesc*) local;
 
   // The TSS moved out of this page. It now carries an I/O permission bitmap
-  // (include/ioperm.h) which does not fit here, and it has to be one object
+  // (include/arch/ioperm.h) which does not fit here, and it has to be one object
   // with it. ioperm_tss() returns it and the descriptor limit that reaches the
   // end of the bitmap.
   tss = (uint*) ioperm_tss(cpunum(), &tsslim);
@@ -136,7 +136,7 @@ seginit(void)
   *(uint64 *) kernel_fs_base = kernel_fs_base;
 
   // Clear the per-CPU slots before anything can read them. Their offsets are
-  // the PERCPU_* constants in include/proc.h and are shared with trapasm.S,
+  // the PERCPU_* constants in include/core/proc.h and are shared with trapasm.S,
   // which reads %gs:24 for proc on the way out to user mode and parks three
   // registers at %gs:32..48 across the FS_BASE swap on the way in.
   ((uint64 *) kernel_fs_base)[2] = 0;      // struct cpu *   (PERCPU_CPU)
@@ -339,7 +339,7 @@ ioremap(uint64 pa, uint64 size)
 
 // --- write-combining, and big buffers -----------------------------------------
 //
-// See include/vmap.h. The console used to draw straight into the framebuffer
+// See include/arch/vmap.h. The console used to draw straight into the framebuffer
 // through the direct map, which is uncached across the whole PCI hole: every
 // store was its own bus transaction and every read -- a scroll is a memmove,
 // so a read for every byte on screen -- waited on the card. In QEMU that is

kernel/arch/x86_64/watch.c

@@ -27,16 +27,16 @@
 // has moved. Worst case a watchpoint takes one tick to cover a CPU, and the
 // cost when nothing has changed is one comparison per tick.
 
-#include "types.h"
-#include "defs.h"
-#include "param.h"
-#include "memlayout.h"
-#include "mmu.h"
-#include "x86.h"
-#include "proc.h"
-#include "traps.h"
-#include "sbuf.h"
-#include "dbg.h"
+#include "core/types.h"
+#include "core/defs.h"
+#include "core/param.h"
+#include "arch/memlayout.h"
+#include "arch/mmu.h"
+#include "arch/x86.h"
+#include "core/proc.h"
+#include "arch/traps.h"
+#include "core/sbuf.h"
+#include "core/dbg.h"
 
 #define NWATCH 4                 // DR0..DR3, and there are no more