Initial commit: Schunix as it stands before the SchOS rename
An x86-64 operating system built from xv6, now largely rewritten: SMP, a copy-on-write root filesystem (SchFS), PCI/USB/virtio drivers, a TTF rasteriser, and a Linux-numbered syscall ABI. No history before this point -- the tree was never under version control. This commit exists so the rename that follows has something to undo to.
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245
kernel/arch/x86_64/lapic.c
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245
kernel/arch/x86_64/lapic.c
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// The local APIC manages internal (non-I/O) interrupts.
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// See Chapter 8 & Appendix C of Intel processor manual volume 3.
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#include "param.h"
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#include "types.h"
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#include "defs.h"
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#include "date.h"
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#include "memlayout.h"
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#include "traps.h"
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#include "mmu.h"
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#include "x86.h"
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#include "proc.h" // ncpu
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// Local APIC registers, divided by 4 for use as uint[] indices.
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#define ID (0x0020/4) // ID
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#define VER (0x0030/4) // Version
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#define TPR (0x0080/4) // Task Priority
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#define EOI (0x00B0/4) // EOI
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#define SVR (0x00F0/4) // Spurious Interrupt Vector
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#define ENABLE 0x00000100 // Unit Enable
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#define ESR (0x0280/4) // Error Status
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#define ICRLO (0x0300/4) // Interrupt Command
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#define SINIT 0x00000500 // INIT/RESET
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#define STARTUP 0x00000600 // Startup IPI
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#define DELIVS 0x00001000 // Delivery status
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#define ASSERT 0x00004000 // Assert interrupt (vs deassert)
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#define LEVEL 0x00008000 // Level triggered
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#define BCAST 0x00080000 // Send to all APICs, including self.
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#define BUSY 0x00001000
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#define ICRHI (0x0310/4) // Interrupt Command [63:32]
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#define TIMER (0x0320/4) // Local Vector Table 0 (TIMER)
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#define X1 0x0000000B // divide counts by 1
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#define PERIODIC 0x00020000 // Periodic
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#define PCINT (0x0340/4) // Performance Counter LVT
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#define LINT0 (0x0350/4) // Local Vector Table 1 (LINT0)
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#define LINT1 (0x0360/4) // Local Vector Table 2 (LINT1)
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#define ERROR (0x0370/4) // Local Vector Table 3 (ERROR)
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#define MASKED 0x00010000 // Interrupt masked
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#define TICR (0x0380/4) // Timer Initial Count
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#define TCCR (0x0390/4) // Timer Current Count
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#define TDCR (0x03E0/4) // Timer Divide Configuration
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volatile uint *lapic; // Initialized in mp.c
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static void
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lapicw(int index, int value)
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{
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lapic[index] = value;
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lapic[ID]; // wait for write to finish, by reading
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}
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void
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lapicinit(void)
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{
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if(!lapic)
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return;
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// Enable local APIC; set spurious interrupt vector.
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lapicw(SVR, ENABLE | (T_IRQ0 + IRQ_SPURIOUS));
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// The timer repeatedly counts down at bus frequency
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// from lapic[TICR] and then issues an interrupt.
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// If xv6 cared more about precise timekeeping,
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// TICR would be calibrated using an external time source.
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lapicw(TDCR, X1);
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lapicw(TIMER, PERIODIC | (T_IRQ0 + IRQ_TIMER));
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lapicw(TICR, 10000000);
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// Disable logical interrupt lines.
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lapicw(LINT0, MASKED);
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lapicw(LINT1, MASKED);
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// Disable performance counter overflow interrupts
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// on machines that provide that interrupt entry.
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if(((lapic[VER]>>16) & 0xFF) >= 4)
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lapicw(PCINT, MASKED);
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// Map error interrupt to IRQ_ERROR.
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lapicw(ERROR, T_IRQ0 + IRQ_ERROR);
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// Clear error status register (requires back-to-back writes).
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lapicw(ESR, 0);
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lapicw(ESR, 0);
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// Ack any outstanding interrupts.
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lapicw(EOI, 0);
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// Send an Init Level De-Assert to synchronise arbitration ID's.
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lapicw(ICRHI, 0);
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lapicw(ICRLO, BCAST | SINIT | LEVEL);
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while(lapic[ICRLO] & DELIVS)
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;
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// Enable interrupts on the APIC (but not on the processor).
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lapicw(TPR, 0);
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}
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int
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cpunum(void)
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{
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int apicid, i;
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// Cannot call cpu when interrupts are enabled:
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// result not guaranteed to last long enough to be used!
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// Would prefer to panic but even printing is chancy here:
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// almost everything, including cprintf and panic, calls cpu,
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// often indirectly through acquire and release.
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if(readeflags()&FL_IF){
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static int n;
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if(n++ == 0)
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cprintf("cpu called from %x with interrupts enabled\n",
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__builtin_return_address(0));
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}
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if (!lapic)
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return 0;
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apicid = lapic[ID] >> 24;
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for (i = 0; i < ncpu; ++i) {
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if (cpus[i].apicid == apicid)
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return i;
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}
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panic("unknown apicid\n");
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}
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// Acknowledge interrupt.
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void
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lapiceoi(void)
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{
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if(lapic)
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lapicw(EOI, 0);
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}
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// Spin for a given number of microseconds.
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// On real hardware would want to tune this dynamically.
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void
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microdelay(int us)
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{
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}
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#define CMOS_PORT 0x70
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#define CMOS_RETURN 0x71
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// Start additional processor running entry code at addr.
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// See Appendix B of MultiProcessor Specification.
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void
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lapicstartap(uchar apicid, uint addr)
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{
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int i;
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ushort *wrv;
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// "The BSP must initialize CMOS shutdown code to 0AH
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// and the warm reset vector (DWORD based at 40:67) to point at
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// the AP startup code prior to the [universal startup algorithm]."
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outb(CMOS_PORT, 0xF); // offset 0xF is shutdown code
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outb(CMOS_PORT+1, 0x0A);
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wrv = (ushort*)P2V((0x40<<4 | 0x67)); // Warm reset vector
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wrv[0] = 0;
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wrv[1] = addr >> 4;
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// "Universal startup algorithm."
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// Send INIT (level-triggered) interrupt to reset other CPU.
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lapicw(ICRHI, apicid<<24);
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lapicw(ICRLO, SINIT | LEVEL | ASSERT);
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microdelay(200);
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lapicw(ICRLO, SINIT | LEVEL);
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microdelay(100); // should be 10ms, but too slow in Bochs!
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// Send startup IPI (twice!) to enter code.
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// Regular hardware is supposed to only accept a STARTUP
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// when it is in the halted state due to an INIT. So the second
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// should be ignored, but it is part of the official Intel algorithm.
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// Bochs complains about the second one. Too bad for Bochs.
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for(i = 0; i < 2; i++){
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lapicw(ICRHI, apicid<<24);
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lapicw(ICRLO, STARTUP | (addr>>12));
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microdelay(200);
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}
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}
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#define CMOS_STATA 0x0a
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#define CMOS_STATB 0x0b
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#define CMOS_UIP (1 << 7) // RTC update in progress
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#define SECS 0x00
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#define MINS 0x02
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#define HOURS 0x04
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#define DAY 0x07
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#define MONTH 0x08
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#define YEAR 0x09
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static uint cmos_read(uint reg)
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{
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outb(CMOS_PORT, reg);
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microdelay(200);
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return inb(CMOS_RETURN);
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}
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static void fill_rtcdate(struct rtcdate *r)
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{
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r->second = cmos_read(SECS);
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r->minute = cmos_read(MINS);
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r->hour = cmos_read(HOURS);
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r->day = cmos_read(DAY);
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r->month = cmos_read(MONTH);
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r->year = cmos_read(YEAR);
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}
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//PAGEBREAK!
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// qemu seems to use 24-hour GWT and the values are BCD encoded
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void cmostime(struct rtcdate *r)
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{
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struct rtcdate t1, t2;
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int sb, bcd;
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sb = cmos_read(CMOS_STATB);
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bcd = (sb & (1 << 2)) == 0;
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// make sure CMOS doesn't modify time while we read it
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for(;;) {
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fill_rtcdate(&t1);
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if(cmos_read(CMOS_STATA) & CMOS_UIP)
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continue;
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fill_rtcdate(&t2);
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if(memcmp(&t1, &t2, sizeof(t1)) == 0)
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break;
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}
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// convert
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if(bcd) {
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#define CONV(x) (t1.x = ((t1.x >> 4) * 10) + (t1.x & 0xf))
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CONV(second);
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CONV(minute);
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CONV(hour );
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CONV(day );
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CONV(month );
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CONV(year );
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#undef CONV
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}
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*r = t1;
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r->year += 2000;
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}
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