Initial commit: Schunix as it stands before the SchOS rename
An x86-64 operating system built from xv6, now largely rewritten: SMP, a copy-on-write root filesystem (SchFS), PCI/USB/virtio drivers, a TTF rasteriser, and a Linux-numbered syscall ABI. No history before this point -- the tree was never under version control. This commit exists so the rename that follows has something to undo to.
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159
kernel/arch/x86_64/mp.c
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159
kernel/arch/x86_64/mp.c
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// Multiprocessor support
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// Search memory for MP description structures.
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// http://developer.intel.com/design/pentium/datashts/24201606.pdf
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#include "types.h"
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#include "defs.h"
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#include "param.h"
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#include "memlayout.h"
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#include "mp.h"
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#include "x86.h"
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#include "mmu.h"
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#include "proc.h"
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struct cpu cpus[NCPU];
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// Processors the firmware says exist.
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int ncpu;
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// Processors actually running, which is not the same number and must not be
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// confused with it. Enumeration is cheap and startup is where the difficulty
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// is: right now the APs are found and deliberately not started, so this stays
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// at 1 while ncpu is 2, 4 or 16.
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//
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// /proc/cpuinfo reports *this* one, matching Linux, where cpuinfo lists online
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// CPUs. Reporting ncpu there told a VM with four processors that it had four
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// working ones, which was a comfortable thing to read and false.
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int ncpu_online = 1;
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uchar ioapicid;
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static uchar
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sum(uchar *addr, int len)
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{
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int i, sum;
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sum = 0;
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for(i=0; i<len; i++)
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sum += addr[i];
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return sum;
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}
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// Look for an MP structure in the len bytes at addr.
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static struct mp*
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mpsearch1(addr_t a, int len)
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{
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uchar *e, *p, *addr;
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addr = P2V(a);
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e = addr+len;
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for(p = addr; p < e; p += sizeof(struct mp))
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if(memcmp(p, "_MP_", 4) == 0 && sum(p, sizeof(struct mp)) == 0)
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return (struct mp*)p;
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return 0;
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}
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// Search for the MP Floating Pointer Structure, which according to the
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// spec is in one of the following three locations:
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// 1) in the first KB of the EBDA;
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// 2) in the last KB of system base memory;
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// 3) in the BIOS ROM between 0xE0000 and 0xFFFFF.
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static struct mp*
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mpsearch(void)
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{
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uchar *bda;
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uint p;
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struct mp *mp;
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bda = (uchar *) P2V(0x400);
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if((p = ((bda[0x0F]<<8)| bda[0x0E]) << 4)){
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if((mp = mpsearch1(p, 1024)))
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return mp;
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} else {
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p = ((bda[0x14]<<8)|bda[0x13])*1024;
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if((mp = mpsearch1(p-1024, 1024)))
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return mp;
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}
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return mpsearch1(0xF0000, 0x10000);
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}
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// Search for an MP configuration table. For now,
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// don't accept the default configurations (physaddr == 0).
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// Check for correct signature, calculate the checksum and,
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// if correct, check the version.
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// To do: check extended table checksum.
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static struct mpconf*
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mpconfig(struct mp **pmp)
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{
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struct mpconf *conf;
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struct mp *mp;
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if((mp = mpsearch()) == 0 || mp->physaddr == 0)
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return 0;
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conf = (struct mpconf*) P2V((addr_t) mp->physaddr);
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if(memcmp(conf, "PCMP", 4) != 0)
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return 0;
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if(conf->version != 1 && conf->version != 4)
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return 0;
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if(sum((uchar*)conf, conf->length) != 0)
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return 0;
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*pmp = mp;
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return conf;
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}
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void
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mpinit(void)
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{
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uchar *p, *e;
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struct mp *mp;
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struct mpconf *conf;
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struct mpproc *mproc;
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struct mpioapic *ioapic;
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if((conf = mpconfig(&mp)) == 0) {
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cprintf("No other CPUs found.\n");
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return;
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}
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lapic = (uint*)P2V(conf->lapicaddr_p);
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for(p=(uchar*)(conf+1), e=(uchar*)conf+conf->length; p<e; ){
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switch(*p){
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case MPPROC:
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mproc = (struct mpproc*)p;
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if(ncpu < NCPU) {
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cpus[ncpu].apicid = mproc->apicid; // apicid may differ from ncpu
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ncpu++;
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}
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p += sizeof(struct mpproc);
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continue;
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case MPIOAPIC:
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ioapic = (struct mpioapic*)p;
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ioapicid = ioapic->apicno;
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p += sizeof(struct mpioapic);
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continue;
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case MPBUS:
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case MPIOINTR:
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case MPLINTR:
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p += 8;
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continue;
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default:
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panic("Major problem parsing mp config.");
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break;
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}
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}
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// "Seems we are" is doing a lot of work here, and the number is usually
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// wrong. This walks the *legacy Intel MP table* (1994), which modern firmware
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// fills in minimally or not at all -- QEMU/SeaBIOS emits exactly one
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// processor entry regardless of -smp, because it expects the OS to enumerate
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// CPUs from the ACPI MADT instead. Verified 2026-08-08: with -smp 4 the table
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// is 208 bytes and contains one type-0 entry, then buses, an I/O APIC and
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// interrupt assignments. So ncpu is 1 on QEMU no matter what, and SMP is
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// silently never exercised there.
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//
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// See docs/roadmap.md "Known broken" -- this is half of the SMP bug, and the
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// reason the other half (AP startup triple-faulting) cannot be reproduced
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// under QEMU until the MADT is parsed.
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cprintf("Seems we are SMP, ncpu = %d\n",ncpu);
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if(mp->imcrp){
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// Bochs doesn't support IMCR, so this doesn't run on Bochs.
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// But it would on real hardware.
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outb(0x22, 0x70); // Select IMCR
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outb(0x23, inb(0x23) | 1); // Mask external interrupts.
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}
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}
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