Initial commit: Schunix as it stands before the SchOS rename
An x86-64 operating system built from xv6, now largely rewritten: SMP, a copy-on-write root filesystem (SchFS), PCI/USB/virtio drivers, a TTF rasteriser, and a Linux-numbered syscall ABI. No history before this point -- the tree was never under version control. This commit exists so the rename that follows has something to undo to.
This commit is contained in:
Nexoniarz
commit
d0f7acf9eb
275 changed files with 51417 additions and 0 deletions
492
kernel/dev/pci.c
Normal file
492
kernel/dev/pci.c
Normal file
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@ -0,0 +1,492 @@
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// PCI bus enumeration.
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//
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// Everything here is done through the two-port configuration mechanism at
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// 0xCF8/0xCFC: write a (bus, slot, function, register) address to one port,
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// read or write the value at the other. It is the oldest and least clever way
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// to reach config space, and it is the one that works everywhere without
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// first having to find an ACPI table to tell you where the memory-mapped
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// version lives.
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//
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// The scan is recursive rather than a flat sweep of all 256 buses. A flat
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// sweep does find everything on a PC, but it also probes 8192 slots that are
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// not there, and it cannot tell you which bridge a device sits behind -- and
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// that matters as soon as interrupt routing does.
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#include "types.h"
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#include "defs.h"
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#include "param.h"
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#include "x86.h"
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#include "spinlock.h"
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#include "sleeplock.h"
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#include "fs.h"
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#include "file.h"
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#include "pci.h"
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#include "device.h"
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static struct pci_dev devs[NPCI];
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static int ndevs;
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static void scan_bus(uint8 bus);
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// ---------------------------------------------------------------------------
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// Configuration space access
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// ---------------------------------------------------------------------------
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static uint32
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cfg_addr(uint8 bus, uint8 slot, uint8 func, uint8 off)
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{
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return 0x80000000u
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| ((uint32)bus << 16)
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| ((uint32)slot << 11)
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| ((uint32)func << 8)
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| (off & 0xFC); // the low two bits are not part of the address
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}
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uint32
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pci_read32(uint8 bus, uint8 slot, uint8 func, uint8 off)
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{
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outl(PCI_CONFIG_ADDR, cfg_addr(bus, slot, func, off));
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return inl(PCI_CONFIG_DATA);
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}
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void
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pci_write32(uint8 bus, uint8 slot, uint8 func, uint8 off, uint32 val)
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{
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outl(PCI_CONFIG_ADDR, cfg_addr(bus, slot, func, off));
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outl(PCI_CONFIG_DATA, val);
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}
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// Config space is only addressable in dwords, so narrower reads are a shift
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// and a mask of the containing dword rather than a narrower bus cycle.
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uint16
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pci_read16(uint8 bus, uint8 slot, uint8 func, uint8 off)
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{
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return (uint16)(pci_read32(bus, slot, func, off) >> ((off & 2) * 8));
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}
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uint8
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pci_read8(uint8 bus, uint8 slot, uint8 func, uint8 off)
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{
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return (uint8)(pci_read32(bus, slot, func, off) >> ((off & 3) * 8));
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}
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void
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pci_enable(struct pci_dev *d, uint16 bits)
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{
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uint32 cmd = pci_read32(d->bus, d->slot, d->func, PCI_COMMAND);
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pci_write32(d->bus, d->slot, d->func, PCI_COMMAND, cmd | bits);
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}
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// ---------------------------------------------------------------------------
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// Capabilities
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//
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// Everything a device can do beyond the 64 bytes of standard config header --
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// MSI, MSI-X, power management, and the whole of virtio's configuration -- is
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// described by a singly linked list of capability structures living in the
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// device's config space. A driver that needs any of it has to walk that list.
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// ---------------------------------------------------------------------------
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// Returns the config-space offset of the first capability with this ID, or 0.
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uint8
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pci_find_cap(struct pci_dev *d, uint8 id)
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{
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uint8 off;
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int guard;
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if(!(pci_read16(d->bus, d->slot, d->func, PCI_STATUS) & PCI_STATUS_CAPLIST))
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return 0;
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off = pci_read8(d->bus, d->slot, d->func, PCI_CAP_PTR) & 0xFC;
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// The list is built by the device, so it can be circular if the device is
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// broken or if we misread it. 48 is more capabilities than the 192 usable
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// bytes can hold; past that we are certainly looping.
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for(guard = 0; off >= 0x40 && guard < 48; guard++){
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if(pci_read8(d->bus, d->slot, d->func, off) == id)
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return off;
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off = pci_read8(d->bus, d->slot, d->func, off + 1) & 0xFC;
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}
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return 0;
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}
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// Point a device's MSI at a CPU and a vector.
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//
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// MSI is not a wire: it is a memory write the device performs to a magic
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// address that the local APIC decodes as an interrupt. That makes it strictly
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// better than INTx for anything modern -- no sharing, no level/edge question,
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// and no chance of the interrupt arriving before the DMA it announces, since
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// both are posted writes travelling the same path in order.
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//
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// Returns 0 on success, -1 if the device has no MSI capability.
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int
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pci_msi_enable(struct pci_dev *d, int vector, int cpu)
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{
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uint8 cap = pci_find_cap(d, PCI_CAP_MSI);
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uint16 ctl;
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if(cap == 0)
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return -1;
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ctl = pci_read16(d->bus, d->slot, d->func, cap + 2);
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// 0xFEE00000 | (apic id << 12) is the LAPIC's message address; the data
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// word is the vector, with delivery mode 000 (fixed) and edge trigger.
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pci_write32(d->bus, d->slot, d->func, cap + 4,
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0xFEE00000u | ((uint32)cpu << 12));
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if(ctl & (1 << 7)){ // 64-bit address capable: data moved to +12
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pci_write32(d->bus, d->slot, d->func, cap + 8, 0);
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pci_write32(d->bus, d->slot, d->func, cap + 12, (uint32)vector);
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} else {
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pci_write32(d->bus, d->slot, d->func, cap + 8, (uint32)vector);
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}
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// Enable, and request exactly one vector (multiple-message-enable = 0).
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// Message control shares its dword with the capability ID and next pointer,
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// and config space is only writable a dword at a time, so read-modify-write
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// the whole thing rather than clobbering the list this capability is on.
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{
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uint32 dw = pci_read32(d->bus, d->slot, d->func, cap);
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ctl = (ctl & ~0x0070) | 1;
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dw = (dw & 0x0000FFFF) | ((uint32)ctl << 16);
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pci_write32(d->bus, d->slot, d->func, cap, dw);
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}
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// INTx must be masked or the device will signal both.
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pci_write32(d->bus, d->slot, d->func, PCI_COMMAND,
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pci_read32(d->bus, d->slot, d->func, PCI_COMMAND) | (1 << 10));
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return 0;
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}
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// ---------------------------------------------------------------------------
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// Base address registers
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// ---------------------------------------------------------------------------
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// A BAR does not report its own size. You find it by writing all ones and
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// reading back: the device leaves the bits it does not decode as zero, so the
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// size is one more than the inverse of what comes back. The original value
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// has to be put back afterwards -- this is a live device whose decoder is
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// briefly pointed at the top of the address space while we look.
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static void
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read_bars(struct pci_dev *d)
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{
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for (int i = 0; i < 6; i++) {
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uint8 off = PCI_BAR0 + i * 4;
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uint32 lo = pci_read32(d->bus, d->slot, d->func, off);
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if (lo == 0)
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continue;
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pci_write32(d->bus, d->slot, d->func, off, 0xFFFFFFFF);
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uint32 mask = pci_read32(d->bus, d->slot, d->func, off);
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pci_write32(d->bus, d->slot, d->func, off, lo);
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if (mask == 0)
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continue;
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if (lo & 1) { // I/O space
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d->bar[i].is_io = 1;
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d->bar[i].base = lo & ~0x3u;
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d->bar[i].size = (~(mask & ~0x3u) + 1) & 0xFFFF;
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continue;
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}
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d->bar[i].prefetch = (lo >> 3) & 1;
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if (((lo >> 1) & 3) == 2) { // 64-bit BAR: eats the next slot
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uint32 hi = pci_read32(d->bus, d->slot, d->func, off + 4);
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pci_write32(d->bus, d->slot, d->func, off + 4, 0xFFFFFFFF);
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uint32 hmask = pci_read32(d->bus, d->slot, d->func, off + 4);
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pci_write32(d->bus, d->slot, d->func, off + 4, hi);
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d->bar[i].is_64 = 1;
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d->bar[i].base = ((uint64)hi << 32) | (lo & ~0xFu);
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d->bar[i].size = ~(((uint64)hmask << 32) | (mask & ~0xFu)) + 1;
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i++; // the upper half is not its own BAR
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continue;
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}
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d->bar[i].base = lo & ~0xFu;
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d->bar[i].size = (~(mask & ~0xFu) + 1) & 0xFFFFFFFF;
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}
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}
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// ---------------------------------------------------------------------------
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// Enumeration
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// ---------------------------------------------------------------------------
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static void
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add_func(uint8 bus, uint8 slot, uint8 func)
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{
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uint16 vendor = pci_read16(bus, slot, func, PCI_VENDOR_ID);
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if (vendor == 0xFFFF) // nothing plugged in
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return;
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if (ndevs >= NPCI) {
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cprintf("pci: more than %d devices, ignoring the rest\n", NPCI);
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return;
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}
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struct pci_dev *d = &devs[ndevs++];
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d->bus = bus;
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d->slot = slot;
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d->func = func;
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d->vendor = vendor;
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d->device = pci_read16(bus, slot, func, PCI_DEVICE_ID);
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d->revision = pci_read8(bus, slot, func, PCI_REVISION);
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d->prog_if = pci_read8(bus, slot, func, PCI_PROG_IF);
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d->subclass = pci_read8(bus, slot, func, PCI_SUBCLASS);
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d->class = pci_read8(bus, slot, func, PCI_CLASS);
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d->header_type = pci_read8(bus, slot, func, PCI_HEADER_TYPE);
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d->irq = pci_read8(bus, slot, func, PCI_INTERRUPT_LINE);
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// Only header type 0 has six BARs. A bridge (type 1) has two and a very
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// different layout, and reading it as though it had six would hand out
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// window registers as if they were device apertures.
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if ((d->header_type & 0x7F) == 0)
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read_bars(d);
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// Walk down through a PCI-to-PCI bridge to whatever is behind it.
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if ((d->header_type & 0x7F) == 1) {
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uint8 secondary = pci_read8(bus, slot, func, PCI_SECONDARY_BUS);
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if (secondary != 0 && secondary != bus)
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scan_bus(secondary);
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}
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}
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static void
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scan_bus(uint8 bus)
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{
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for (uint8 slot = 0; slot < 32; slot++) {
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if (pci_read16(bus, slot, 0, PCI_VENDOR_ID) == 0xFFFF)
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continue;
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add_func(bus, slot, 0);
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// Bit 7 of the header type says the device has more than one function.
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// Probing all eight unconditionally is harmless on real hardware but
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// produces phantom entries on some emulated devices, which answer every
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// function with a copy of function 0.
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if (pci_read8(bus, slot, 0, PCI_HEADER_TYPE) & 0x80)
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for (uint8 func = 1; func < 8; func++)
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add_func(bus, slot, func);
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}
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}
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// ---------------------------------------------------------------------------
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// Lookup
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// ---------------------------------------------------------------------------
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int
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pci_count(void)
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{
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return ndevs;
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}
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struct pci_dev *
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pci_get(int i)
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{
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return (i >= 0 && i < ndevs) ? &devs[i] : 0;
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}
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struct pci_dev *
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pci_find_class(uint8 class, uint8 subclass)
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{
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for (int i = 0; i < ndevs; i++)
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if (devs[i].class == class && devs[i].subclass == subclass)
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return &devs[i];
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return 0;
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}
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struct pci_dev *
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pci_find_id(uint16 vendor, uint16 device)
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{
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for (int i = 0; i < ndevs; i++)
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if (devs[i].vendor == vendor && devs[i].device == device)
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return &devs[i];
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return 0;
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}
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// ---------------------------------------------------------------------------
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// Driver binding
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// ---------------------------------------------------------------------------
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static int
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matches(const struct pci_match *m, struct pci_dev *d)
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{
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if (m->vendor != PCI_ANY)
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return m->vendor == d->vendor &&
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(m->device == PCI_ANY || m->device == d->device);
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// A class match, for drivers that handle a kind of device rather than a
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// particular model.
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return m->class == d->class &&
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(m->subclass == 0xFF || m->subclass == d->subclass);
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}
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// Offer every unclaimed device to a driver. Called by pci_init() for each
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// entry in the registry; see kernel/drivers/registry.c.
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// Defined further down with the /proc/pci formatting it was written for.
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static const char *class_name(uint8 class, uint8 subclass);
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// Translate a PCI class code into the bus-agnostic one the device model uses.
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//
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// The two vocabularies are deliberately separate. PCI's class byte describes
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// how the card presents itself on that bus; DEVCLASS describes what the rest of
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// the kernel can *do* with it, and a USB disk has to land in the same bucket as
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// a SATA one despite sharing no numbering with it at all.
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enum dev_class
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pci_class_of(const struct pci_dev *d)
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{
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switch (d->class) {
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case PCI_CLASS_DISPLAY: return DEVCLASS_DISPLAY;
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case PCI_CLASS_STORAGE: return DEVCLASS_STORAGE;
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case PCI_CLASS_NETWORK: return DEVCLASS_NET;
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case PCI_CLASS_SERIAL_BUS: return DEVCLASS_BUS;
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default: return DEVCLASS_OTHER;
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}
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}
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// Human-readable description, the same text /proc/pci prints for the device.
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void
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pci_describe(const struct pci_dev *d, char *out, int cap)
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{
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const char *s = class_name(d->class, d->subclass);
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int n = 0;
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while (s[n] && n < cap - 1) {
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out[n] = s[n];
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n++;
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}
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out[n] = '\0';
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}
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void
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pci_bind(const struct pci_driver *drv)
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{
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for (int i = 0; i < ndevs; i++) {
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struct pci_dev *d = &devs[i];
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if (d->driver)
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continue;
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for (const struct pci_match *m = drv->match; m->vendor || m->class; m++) {
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if (!matches(m, d))
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continue;
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if (drv->probe(d) == 0) {
|
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d->driver = drv->name;
|
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// Publish it in the bus-agnostic device list. Done here rather than in
|
||||
// each driver's probe() so that a driver cannot forget to, and so the
|
||||
// list is populated in bind order -- which is the order a device
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// manager should show.
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struct device *dev = device_add(drv->devname ? drv->devname : drv->name,
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DEVBUS_PCI, pci_class_of(d), drv->name);
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if (dev) {
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dev->ops = (void *)drv->ops;
|
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dev->vendor = d->vendor;
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dev->product = d->device;
|
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dev->b = d->bus; dev->s = d->slot; dev->f = d->func;
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pci_describe(d, dev->desc, sizeof(dev->desc));
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}
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}
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break;
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}
|
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}
|
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}
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
// Fixed-width lowercase hex, the way lspci prints addresses.
|
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static int
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put_hex(char *out, uint64 v, int digits)
|
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{
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static const char d[] = "0123456789abcdef";
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for (int i = digits - 1; i >= 0; i--)
|
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*out++ = d[(v >> (i * 4)) & 0xF];
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return digits;
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}
|
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static int
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||||
put_str(char *out, const char *s)
|
||||
{
|
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int n = 0;
|
||||
while (s[n]) { out[n] = s[n]; n++; }
|
||||
return n;
|
||||
}
|
||||
|
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static const char *
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class_name(uint8 class, uint8 subclass)
|
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{
|
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switch (class) {
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case PCI_CLASS_STORAGE:
|
||||
return subclass == 0x01 ? "IDE controller"
|
||||
: subclass == 0x06 ? "SATA controller"
|
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: subclass == 0x08 ? "NVMe controller"
|
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: "storage controller";
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||||
case PCI_CLASS_NETWORK: return "network controller";
|
||||
case PCI_CLASS_DISPLAY: return "display controller";
|
||||
case PCI_CLASS_MULTIMEDIA: return "multimedia device";
|
||||
case PCI_CLASS_BRIDGE:
|
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return subclass == 0x00 ? "host bridge"
|
||||
: subclass == 0x01 ? "ISA bridge"
|
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: subclass == 0x04 ? "PCI bridge"
|
||||
: "bridge";
|
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case PCI_CLASS_SERIAL_BUS:
|
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return subclass == 0x03 ? "USB controller" : "serial bus controller";
|
||||
}
|
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return "device";
|
||||
}
|
||||
|
||||
// Fills a buffer for /proc/pci. Returns bytes written.
|
||||
//
|
||||
// There is no snprintf in the kernel, so this appends by hand in the same
|
||||
// style as kernel/dev/procfs.c. The output is deliberately lspci-shaped --
|
||||
// "bus:slot.func vendor:device description" -- because that is the format
|
||||
// anyone reading it will already know how to scan.
|
||||
int
|
||||
pci_info(char *buf, int cap)
|
||||
{
|
||||
int len = 0;
|
||||
|
||||
for (int i = 0; i < ndevs; i++) {
|
||||
struct pci_dev *d = &devs[i];
|
||||
|
||||
if (len > cap - 96) // room for one more line
|
||||
break;
|
||||
|
||||
len += put_hex(buf + len, d->bus, 2);
|
||||
buf[len++] = ':';
|
||||
len += put_hex(buf + len, d->slot, 2);
|
||||
buf[len++] = '.';
|
||||
len += put_hex(buf + len, d->func, 1);
|
||||
buf[len++] = ' ';
|
||||
len += put_hex(buf + len, d->vendor, 4);
|
||||
buf[len++] = ':';
|
||||
len += put_hex(buf + len, d->device, 4);
|
||||
buf[len++] = ' ';
|
||||
len += put_str(buf + len, class_name(d->class, d->subclass));
|
||||
len += put_str(buf + len, " [");
|
||||
len += put_str(buf + len, d->driver ? d->driver : "-");
|
||||
buf[len++] = ']';
|
||||
buf[len++] = '\n';
|
||||
}
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
void
|
||||
pci_init(void)
|
||||
{
|
||||
ndevs = 0;
|
||||
|
||||
// If there is no host bridge at 0:0.0 there is no PCI, and every config
|
||||
// read will come back 0xFFFFFFFF. Saying so once beats 8192 silent probes.
|
||||
if (pci_read16(0, 0, 0, PCI_VENDOR_ID) == 0xFFFF) {
|
||||
cprintf("pci: no host bridge; bus not present\n");
|
||||
return;
|
||||
}
|
||||
|
||||
scan_bus(0);
|
||||
cprintf("pci: %d device%s\n", ndevs, ndevs == 1 ? "" : "s");
|
||||
|
||||
pci_bind_all();
|
||||
}
|
||||
Loading…
Reference in a new issue