Initial commit: Schunix as it stands before the SchOS rename
An x86-64 operating system built from xv6, now largely rewritten: SMP, a copy-on-write root filesystem (SchFS), PCI/USB/virtio drivers, a TTF rasteriser, and a Linux-numbered syscall ABI. No history before this point -- the tree was never under version control. This commit exists so the rename that follows has something to undo to.
This commit is contained in:
Nexoniarz
commit
d0f7acf9eb
275 changed files with 51417 additions and 0 deletions
456
kernel/drivers/net/e1000/e1000.c
Normal file
456
kernel/drivers/net/e1000/e1000.c
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// Intel 8254x gigabit Ethernet, written from Intel's public datasheet (317453).
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//
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// The first network device. There is no IP stack yet, so what this provides is
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// the layer under one: a MAC address, a transmit path, and a receive ring that
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// fills with frames. That is deliberately the right order -- an IP stack
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// written before a driver has nothing to be tested against, and every bug in it
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// looks like a driver bug.
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//
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// Bring-up follows the manual's initialisation sequence (section 14.3-14.5):
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// reset, read the MAC out of EEPROM, clear the multicast table, set up the
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// receive and transmit rings, then enable each. The order matters -- enabling a
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// receiver whose ring base is still zero makes the device DMA into physical
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// address 0, which on this kernel is the boot page table.
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#include "types.h"
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#include "defs.h"
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#include "param.h"
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#include "x86.h"
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#include "spinlock.h"
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#include "sleeplock.h"
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#include "fs.h"
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#include "file.h"
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#include "mmu.h"
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#include "memlayout.h"
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#include "pci.h"
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#include "device.h"
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#include "dma.h"
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#include "irq.h"
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#include "e1000.h"
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struct e1000 {
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volatile uint8 *regs;
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struct e1000_tx_desc *tx;
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struct e1000_rx_desc *rx;
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uint8 *txbuf[E1000_NTX];
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uint8 *rxbuf[E1000_NRX];
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uint16 tx_next;
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uint16 rx_next;
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uint8 mac[6];
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int ready;
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uint64 rx_packets, tx_packets, rx_dropped;
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struct spinlock lock;
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};
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static struct e1000 nic;
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static inline uint32 rd(struct e1000 *e, int off) { return *(volatile uint32 *)(e->regs + off); }
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static inline void wr(struct e1000 *e, int off, uint32 v) { *(volatile uint32 *)(e->regs + off) = v; }
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// The EEPROM is read one 16-bit word at a time through a single register: write
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// the address with the start bit, poll for done, take the data out of the top
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// half.
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//
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// Bounded, because a device whose EEPROM never reports done would otherwise
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// hang the boot -- and QEMU's e1000 does answer, but a real card with a blank
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// EEPROM is a thing that exists.
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static int
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eeprom_read(struct e1000 *e, int addr, uint16 *out)
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{
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wr(e, E1000_EERD, (addr << E1000_EERD_ADDR_SHIFT) | E1000_EERD_START);
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for (int i = 0; i < 100000; i++) {
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uint32 v = rd(e, E1000_EERD);
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if (v & E1000_EERD_DONE) {
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*out = (uint16)(v >> E1000_EERD_DATA_SHIFT);
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return 0;
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}
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}
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return -1;
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}
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// The MAC address, from EEPROM words 0..2, little-endian within each word.
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//
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// Falls back to the receive-address registers, which the firmware may already
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// have programmed. QEMU fills both; some cards leave the EEPROM path
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// unimplemented, and a driver that only knows one of the two ends up with a MAC
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// of all zeroes and no idea why nothing answers it.
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static void
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read_mac(struct e1000 *e)
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{
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uint16 w;
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int ok = 1;
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for (int i = 0; i < 3; i++) {
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if (eeprom_read(e, i, &w) != 0) { ok = 0; break; }
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e->mac[i * 2] = (uint8)(w & 0xFF);
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e->mac[i * 2 + 1] = (uint8)(w >> 8);
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}
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if (ok)
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return;
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uint32 lo = rd(e, E1000_RAL), hi = rd(e, E1000_RAH);
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e->mac[0] = (uint8)lo; e->mac[1] = (uint8)(lo >> 8);
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e->mac[2] = (uint8)(lo >> 16); e->mac[3] = (uint8)(lo >> 24);
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e->mac[4] = (uint8)hi; e->mac[5] = (uint8)(hi >> 8);
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}
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static int
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rings_setup(struct e1000 *e)
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{
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// One block for both rings and every buffer, from the DMA arena: the device
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// reads all of it by physical address, and kalloc's pages are contiguous only
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// by accident.
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uint32 txring = E1000_NTX * sizeof(struct e1000_tx_desc);
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uint32 rxring = E1000_NRX * sizeof(struct e1000_rx_desc);
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e->tx = dma_alloc(txring, 16);
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e->rx = dma_alloc(rxring, 16);
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if (!e->tx || !e->rx)
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return -1;
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memset(e->tx, 0, txring);
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memset(e->rx, 0, rxring);
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for (int i = 0; i < E1000_NTX; i++) {
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e->txbuf[i] = dma_alloc(E1000_BUFSZ, 16);
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if (!e->txbuf[i])
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return -1;
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e->tx[i].addr = dma_phys(e->txbuf[i]);
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// DD set on every transmit descriptor at start-up, so the first pass round
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// the ring sees them as free. The hardware only sets it after it has used
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// one, and a driver that waits for a bit the device has never had reason to
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// write waits forever.
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e->tx[i].status = E1000_TXD_STAT_DD;
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}
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for (int i = 0; i < E1000_NRX; i++) {
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e->rxbuf[i] = dma_alloc(E1000_BUFSZ, 16);
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if (!e->rxbuf[i])
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return -1;
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e->rx[i].addr = dma_phys(e->rxbuf[i]);
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e->rx[i].status = 0;
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}
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wr(e, E1000_TDBAL, (uint32)dma_phys(e->tx));
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wr(e, E1000_TDBAH, (uint32)(dma_phys(e->tx) >> 32));
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wr(e, E1000_TDLEN, txring);
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wr(e, E1000_TDH, 0);
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wr(e, E1000_TDT, 0);
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wr(e, E1000_RDBAL, (uint32)dma_phys(e->rx));
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wr(e, E1000_RDBAH, (uint32)(dma_phys(e->rx) >> 32));
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wr(e, E1000_RDLEN, rxring);
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wr(e, E1000_RDH, 0);
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// Tail points at the last descriptor the hardware may fill. Setting it to
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// NRX-1 hands it every descriptor but one; the ring is full when head meets
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// tail, so one must always be held back or "full" and "empty" look identical.
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wr(e, E1000_RDT, E1000_NRX - 1);
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return 0;
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}
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// Queue one frame. Returns 0, or -1 if the ring is full.
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//
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// Copies into the descriptor's own buffer rather than mapping the caller's.
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// A zero-copy path wants the caller to guarantee the memory stays put and is
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// physically contiguous, which nothing above this can promise yet.
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int
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e1000_transmit(const void *frame, int len)
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{
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struct e1000 *e = &nic;
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if (!e->ready || len <= 0 || len > E1000_BUFSZ)
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return -1;
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acquire(&e->lock);
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struct e1000_tx_desc *d = &e->tx[e->tx_next];
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if (!(d->status & E1000_TXD_STAT_DD)) {
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release(&e->lock);
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return -1; // the device has not finished with it
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}
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memmove(e->txbuf[e->tx_next], frame, len);
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d->length = (uint16)len;
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d->cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS | E1000_TXD_CMD_RS;
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d->status = 0;
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e->tx_next = (uint16)((e->tx_next + 1) % E1000_NTX);
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__sync_synchronize(); // descriptor visible before the tail moves
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wr(e, E1000_TDT, e->tx_next);
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e->tx_packets++;
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release(&e->lock);
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return 0;
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}
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// Take one received frame, if there is one. Returns its length, or 0.
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//
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// Polled. There is nothing above this to wake yet, and a receive path that
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// wakes a nonexistent protocol stack is harder to reason about than one that is
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// asked. The interrupt handler below exists to keep the cause register clear
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// and to count; when an IP stack arrives, this is where the hand-off changes.
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int
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e1000_receive(void *out, int cap)
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{
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struct e1000 *e = &nic;
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if (!e->ready)
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return 0;
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acquire(&e->lock);
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struct e1000_rx_desc *d = &e->rx[e->rx_next];
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if (!(d->status & E1000_RXD_STAT_DD)) {
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release(&e->lock);
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return 0;
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}
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int len = d->length;
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if (len > cap)
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len = cap;
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memmove(out, e->rxbuf[e->rx_next], len);
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d->status = 0;
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__sync_synchronize();
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// Hand the descriptor back by moving the tail to it. The tail always trails
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// the descriptor just released, which is why it is the *previous* index.
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wr(e, E1000_RDT, e->rx_next);
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e->rx_next = (uint16)((e->rx_next + 1) % E1000_NRX);
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e->rx_packets++;
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release(&e->lock);
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return len;
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}
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static void
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e1000_intr(void *arg)
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{
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struct e1000 *e = arg;
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// Reading ICR clears it. Not reading it leaves the cause asserted, and with a
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// level-triggered PCI interrupt that means the handler is re-entered forever.
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uint32 cause = rd(e, E1000_ICR);
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(void)cause;
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}
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int
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e1000_info(char *buf, int cap)
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{
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struct e1000 *e = &nic;
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int n = 0;
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if (!e->ready)
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return 0;
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static const char hex[] = "0123456789abcdef";
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n += 0;
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for (int i = 0; i < 6 && n + 3 < cap; i++) {
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buf[n++] = hex[e->mac[i] >> 4];
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buf[n++] = hex[e->mac[i] & 0xF];
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if (i < 5)
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buf[n++] = ':';
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}
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if (n < cap) buf[n++] = '\n';
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return n;
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}
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static int
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e1000_probe(struct pci_dev *d)
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{
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struct e1000 *e = &nic;
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if (e->ready)
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return -1;
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if (!d->bar[0].base)
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return -1;
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initlock(&e->lock, "e1000");
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pci_enable(d, 0x0006); // memory space + bus master
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e->regs = (volatile uint8 *)P2V(d->bar[0].base);
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// Reset, then wait for it to clear. The manual asks for a delay after reset
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// before any other register is touched; polling CTRL is that delay.
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wr(e, E1000_CTRL, rd(e, E1000_CTRL) | E1000_CTRL_RST);
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for (int i = 0; i < 1000000; i++)
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if (!(rd(e, E1000_CTRL) & E1000_CTRL_RST))
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break;
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wr(e, E1000_IMC, 0xFFFFFFFF); // mask everything while we set up
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rd(e, E1000_ICR); // and clear whatever was pending
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wr(e, E1000_CTRL, rd(e, E1000_CTRL) | E1000_CTRL_SLU | E1000_CTRL_ASDE);
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read_mac(e);
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// The multicast table is undefined after reset. Left as it comes up, the
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// device accepts multicast traffic for addresses nobody asked for.
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for (int i = 0; i < 128; i++)
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wr(e, E1000_MTA + i * 4, 0);
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// Program our own MAC into the receive-address filter, with the valid bit.
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{
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uint32 lo = (uint32)e->mac[0] | ((uint32)e->mac[1] << 8) |
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((uint32)e->mac[2] << 16) | ((uint32)e->mac[3] << 24);
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uint32 hi = (uint32)e->mac[4] | ((uint32)e->mac[5] << 8) | (1u << 31);
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wr(e, E1000_RAL, lo);
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wr(e, E1000_RAH, hi);
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}
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if (rings_setup(e) != 0) {
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cprintf("e1000: no DMA memory for the rings\n");
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return -1;
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}
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wr(e, E1000_TIPG, 10 | (8 << 10) | (6 << 20)); // the manual's IEEE defaults
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wr(e, E1000_TCTL, E1000_TCTL_EN | E1000_TCTL_PSP |
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(0x10 << E1000_TCTL_CT_SHIFT) |
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(0x40 << E1000_TCTL_COLD_SHIFT));
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wr(e, E1000_RCTL, E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SECRC |
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E1000_RCTL_SZ_2048 | E1000_RCTL_LBM_NONE);
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if (d->irq != 0xFF)
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// level_low = 1: this is a PCI interrupt, which is level-triggered and
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// active low. Registering it as edge-triggered makes it fire once and then
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// wedge, because the device holds the line asserted and no further edge
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// ever arrives. See the comment on irq_register in include/irq.h.
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irq_register(d->irq, e1000_intr, e, "e1000", 1);
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wr(e, E1000_IMS, E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_LSC);
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e->ready = 1;
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cprintf("e1000: %x:%x:%x:%x:%x:%x, link %s, irq %d\n",
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e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5],
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(rd(e, E1000_STATUS) & E1000_STATUS_LU) ? "up" : "down", d->irq);
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return 0;
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}
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// Every 8254x that shares the register map above. See include/e1000.h for
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// where the IDs come from and why the PCIe parts are excluded.
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#define M(id) { E1000_VENDOR, (id), 0, 0 }
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static const struct pci_match e1000_match[] = {
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M(E1000_DEV_82540EM), M(E1000_DEV_82540EM_LOM),
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M(E1000_DEV_82540EP_LOM), M(E1000_DEV_82540EP),
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M(E1000_DEV_82540EP_LP),
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M(E1000_DEV_82541EI), M(E1000_DEV_82541EI_MOBILE),
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M(E1000_DEV_82541ER_LOM), M(E1000_DEV_82541ER),
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M(E1000_DEV_82541GI), M(E1000_DEV_82541GI_MOBILE),
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M(E1000_DEV_82541GI_LF),
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M(E1000_DEV_82544EI_FIBER), M(E1000_DEV_82544GC_COPPER),
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M(E1000_DEV_82544GC_LOM),
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M(E1000_DEV_82545EM_COPPER), M(E1000_DEV_82545EM_FIBER),
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M(E1000_DEV_82545GM_COPPER), M(E1000_DEV_82545GM_FIBER),
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M(E1000_DEV_82545GM_SERDES),
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M(E1000_DEV_82546EB_COPPER), M(E1000_DEV_82546EB_FIBER),
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M(E1000_DEV_82546EB_QUAD),
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M(E1000_DEV_82546GB_COPPER), M(E1000_DEV_82546GB_FIBER),
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M(E1000_DEV_82546GB_SERDES),
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M(E1000_DEV_82547EI),
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{ 0, 0, 0, 0 },
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};
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#undef M
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const struct pci_driver e1000_driver = {
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.name = "e1000",
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.devname = "eth",
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.match = e1000_match,
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.ops = 0, // no class vtable yet; there is no net class
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.probe = e1000_probe,
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};
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// --- self-test: does this thing actually move packets? ---------------------
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//
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// The transmit and receive paths were written together and neither had ever
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// carried a frame. That is exactly the state in which a driver looks finished
|
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// and is not: the rings are set up, the registers read back plausibly, and the
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// first thing to discover otherwise would have been a protocol stack failing
|
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// for reasons indistinguishable from its own bugs.
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//
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// So: build an ARP request by hand, send it, and wait for the reply. It proves
|
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// the whole path at once -- descriptor format, DD handshake, tail bookkeeping,
|
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// DMA addresses, the receive ring handback, and the MAC filter -- because an
|
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// ARP reply is addressed to *us* and will not arrive if the filter is wrong.
|
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//
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// Under QEMU's user-mode networking the guest is 10.0.2.15 and the gateway is
|
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// 10.0.2.2. SLIRP is silent until spoken to, which is why this has to transmit
|
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// before it can expect to receive.
|
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//
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// `echo n > /proc/sysrq`.
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static void
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put_be16(uint8 *p, uint16 v)
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{
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p[0] = (uint8)(v >> 8);
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p[1] = (uint8)v;
|
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}
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const unsigned char *
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e1000_mac(void)
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{
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return nic.mac;
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}
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void
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e1000_selftest(void)
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{
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struct e1000 *e = &nic;
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||||
uint8 frame[42];
|
||||
uint8 reply[E1000_BUFSZ];
|
||||
|
||||
if (!e->ready) {
|
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cprintf("e1000: no device\n");
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return;
|
||||
}
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||||
|
||||
static const uint8 me[4] = { 10, 0, 2, 15 }; // QEMU SLIRP guest address
|
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static const uint8 them[4] = { 10, 0, 2, 2 }; // and its gateway
|
||||
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memset(frame, 0, sizeof(frame));
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||||
for (int i = 0; i < 6; i++)
|
||||
frame[i] = 0xFF; // broadcast
|
||||
for (int i = 0; i < 6; i++)
|
||||
frame[6 + i] = e->mac[i];
|
||||
put_be16(&frame[12], 0x0806); // ARP
|
||||
|
||||
put_be16(&frame[14], 1); // Ethernet
|
||||
put_be16(&frame[16], 0x0800); // IPv4
|
||||
frame[18] = 6; // hardware address length
|
||||
frame[19] = 4; // protocol address length
|
||||
put_be16(&frame[20], 1); // request
|
||||
for (int i = 0; i < 6; i++)
|
||||
frame[22 + i] = e->mac[i]; // sender hardware address
|
||||
for (int i = 0; i < 4; i++)
|
||||
frame[28 + i] = me[i]; // sender protocol address
|
||||
// target hardware address stays zero -- that is what is being asked
|
||||
for (int i = 0; i < 4; i++)
|
||||
frame[38 + i] = them[i];
|
||||
|
||||
cprintf("e1000: asking who has %d.%d.%d.%d\n", them[0], them[1], them[2], them[3]);
|
||||
if (e1000_transmit(frame, sizeof(frame)) != 0) {
|
||||
cprintf("e1000: transmit ring full\n");
|
||||
return;
|
||||
}
|
||||
|
||||
// Bounded poll. There is no interrupt path to sleep on yet and this runs from
|
||||
// a sysrq write, so spinning briefly is the honest way to wait.
|
||||
for (int spin = 0; spin < 20000000; spin++) {
|
||||
int n = e1000_receive(reply, sizeof(reply));
|
||||
if (n <= 0)
|
||||
continue;
|
||||
|
||||
cprintf("e1000: %d bytes from %x:%x:%x:%x:%x:%x type %x\n",
|
||||
n, reply[6], reply[7], reply[8], reply[9], reply[10], reply[11],
|
||||
((uint32)reply[12] << 8) | reply[13]);
|
||||
|
||||
if (n >= 42 && reply[12] == 0x08 && reply[13] == 0x06 &&
|
||||
reply[20] == 0 && reply[21] == 2) {
|
||||
cprintf("e1000: ARP reply -- %d.%d.%d.%d is at %x:%x:%x:%x:%x:%x\n",
|
||||
reply[28], reply[29], reply[30], reply[31],
|
||||
reply[22], reply[23], reply[24], reply[25],
|
||||
reply[26], reply[27]);
|
||||
cprintf("e1000: self-test passed, %d tx %d rx\n",
|
||||
(int)e->tx_packets, (int)e->rx_packets);
|
||||
return;
|
||||
}
|
||||
}
|
||||
cprintf("e1000: no reply -- %d tx, %d rx\n",
|
||||
(int)e->tx_packets, (int)e->rx_packets);
|
||||
}
|
||||
Loading…
Reference in a new issue