kernel: laptop touchpads over I2C-HID
A laptop's touchpad is on the chipset's I2C bus, found only through ACPI (PNP0C50 / ACPI0C50), and SchOS had no I2C at all, so the touchpad of every recent laptop did nothing. kernel/acpi/i2c_hid.c drives the DesignWare I2C controller every x86 chipset uses (AMDI0010 on Ryzen) by polling, speaks HID over I2C to the device the _DSM points at, and feeds the reports through the USB HID parser. On AMD the interrupt pin's level is read every tick, so a report is read exactly when one is waiting; elsewhere the input register is polled. The touchpad is driven in mouse mode, which it starts in after a reset: motion, clicks and taps become /dev/input/event1 like any mouse. The HID parser now prefers a descriptor's relative pointer over an absolute one for this, and takes descriptors from transports other than USB. Untested on hardware: QEMU emulates no I2C touchpad. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01S1giNvrHTrPMPw7V6x1kQ4
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Nexoniarz
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5 changed files with 733 additions and 15 deletions
635
kernel/acpi/i2c_hid.c
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635
kernel/acpi/i2c_hid.c
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// SPDX-License-Identifier: GPL-2.0-or-later
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//
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// Laptop touchpads: HID over I2C, on the SoC's DesignWare I2C controller.
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//
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// A laptop's touchpad is not on PS/2 any more and not on USB either. It hangs
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// off an I2C bus inside the chipset, and the only place that says so is ACPI:
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// a device whose _HID or _CID is PNP0C50, with an I2cSerialBus resource
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// naming the controller and the touchpad's address, a GpioInt naming the pin
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// it pulls when it has something to say, and a _DSM giving the one register
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// number the protocol needs to bootstrap itself. Without this the touchpad of
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// every recent laptop -- the ASUS TUF A15's included -- does nothing at all.
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//
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// Three layers, all here because each is small:
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//
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// The controller. Every x86 chipset since Haswell, AMD's included, uses the
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// same Synopsys DesignWare I2C block (AMDI0010 on Ryzen, INT33C3, INT3433
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// and the PCI LPSS functions on Intel). Driven by polling: a touchpad report
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// is about 30 bytes, a millisecond on the bus.
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//
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// HID over I2C (Microsoft's specification, version 1.0). Read the HID
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// descriptor from the register _DSM names; power the device on and reset
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// it; read the report descriptor; then every input report is a read of the
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// input register, two bytes of length and the report.
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//
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// The interrupt line. It is level-triggered and stays asserted for as long
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// as a report is waiting, so instead of routing it through the GPIO
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// controller's interrupt the pin's *level* is read, every tick: low means
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// read a report. That is exact -- no report is read twice and none is
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// missed -- and needs nothing from the GPIO controller but its registers.
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// On AMD those are one 32-bit word per pin. Elsewhere there is no pin to
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// watch, and the input register is simply read every tick; devices answer
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// a read with nothing waiting with a zero length.
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//
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// The reports themselves go through the USB HID driver's parser and pointer
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// path (include/dev/hid.h). A Windows Precision Touchpad starts in mouse mode
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// after a reset -- relative motion, a button for a click and for a tap -- and
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// that is the report taken: it is what makes it a mouse on /dev/input/event1,
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// for the console and for X. Multi-finger reports (two-finger scroll) need the
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// device switched to touchpad mode and a gesture layer; not yet.
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#include "core/types.h"
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#include "core/defs.h"
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#include "core/param.h"
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#include "core/spinlock.h"
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#include "arch/mmu.h"
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#include "dev/hid.h"
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#include "dev/acpi.h"
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#include <uacpi/uacpi.h>
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#include <uacpi/utilities.h>
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#include <uacpi/namespace.h>
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#include <uacpi/resources.h>
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// ---------------------------------------------------------------------------
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// DesignWare I2C
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// ---------------------------------------------------------------------------
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#define IC_CON 0x00
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#define IC_TAR 0x04
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#define IC_DATA_CMD 0x10
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#define IC_SS_SCL_HCNT 0x14
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#define IC_SS_SCL_LCNT 0x18
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#define IC_FS_SCL_HCNT 0x1C
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#define IC_FS_SCL_LCNT 0x20
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#define IC_INTR_MASK 0x30
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#define IC_RAW_INTR_STAT 0x34
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#define IC_RX_TL 0x38
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#define IC_TX_TL 0x3C
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#define IC_CLR_INTR 0x40
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#define IC_CLR_TX_ABRT 0x54
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#define IC_CLR_STOP_DET 0x60
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#define IC_ENABLE 0x6C
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#define IC_STATUS 0x70
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#define IC_TXFLR 0x74
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#define IC_RXFLR 0x78
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#define IC_SDA_HOLD 0x7C
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#define IC_TX_ABRT_SOURCE 0x80
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#define IC_ENABLE_STATUS 0x9C
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#define IC_COMP_PARAM_1 0xF4
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#define IC_COMP_TYPE 0xFC
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#define DW_COMP_TYPE 0x44570140
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#define CON_MASTER (1 << 0)
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#define CON_SPEED_STD (1 << 1)
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#define CON_SPEED_FAST (2 << 1)
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#define CON_RESTART_EN (1 << 5)
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#define CON_SLAVE_DISABLE (1 << 6)
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#define CMD_READ (1 << 8)
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#define CMD_STOP (1 << 9)
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#define CMD_RESTART (1 << 10)
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#define INTR_TX_ABRT (1 << 6)
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#define INTR_STOP_DET (1 << 9)
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#define NCTL 4
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struct dwi2c {
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uint64 phys;
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volatile uint32 *regs;
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int txdepth, rxdepth;
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int fast;
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};
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static struct dwi2c ctls[NCTL];
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static int nctl;
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static uint32
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rd(struct dwi2c *c, int reg)
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{
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return c->regs[reg / 4];
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}
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static void
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wr(struct dwi2c *c, int reg, uint32 v)
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{
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c->regs[reg / 4] = v;
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}
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static int
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dw_enable(struct dwi2c *c, int on)
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{
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int i;
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for(i = 0; i < 1000; i++){
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wr(c, IC_ENABLE, on);
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if((rd(c, IC_ENABLE_STATUS) & 1) == (uint32)on)
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return 0;
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microdelay(25);
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}
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return -1;
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}
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// SCL high and low periods, in controller clocks, from the firmware's own
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// numbers when it gives them: SSCN and FMCN are packages of (HCNT, LCNT,
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// SDA hold) for exactly this controller's clock.
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static int
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acpi_counts(uacpi_namespace_node *node, const char *name,
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uint32 *hcnt, uint32 *lcnt, uint32 *hold)
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{
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uacpi_object *o = 0;
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uacpi_object_array a;
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uacpi_u64 v[3];
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int i;
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if(uacpi_eval_package(node, name, 0, &o) != UACPI_STATUS_OK)
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return -1;
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if(uacpi_object_get_package(o, &a) != UACPI_STATUS_OK || a.count < 2){
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uacpi_object_unref(o);
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return -1;
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}
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v[2] = 0;
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for(i = 0; i < 3 && i < (int)a.count; i++)
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if(uacpi_object_get_integer(a.objects[i], &v[i]) != UACPI_STATUS_OK){
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uacpi_object_unref(o);
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return -1;
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}
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uacpi_object_unref(o);
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*hcnt = v[0];
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*lcnt = v[1];
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*hold = v[2];
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return 0;
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}
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static int
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dw_init(struct dwi2c *c, uacpi_namespace_node *node, uint32 speed)
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{
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uint32 type, param, hcnt, lcnt, hold = 0;
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c->regs = ioremap(c->phys, 0x1000);
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if(c->regs == 0)
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return -1;
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type = rd(c, IC_COMP_TYPE);
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if(type != DW_COMP_TYPE){
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cprintf("i2c: controller at 0x%lx is not DesignWare (0x%x)\n",
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c->phys, type);
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return -1;
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}
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param = rd(c, IC_COMP_PARAM_1);
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c->txdepth = param ? ((param >> 16) & 0xFF) + 1 : 8;
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c->rxdepth = param ? ((param >> 8) & 0xFF) + 1 : 8;
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c->fast = speed >= 400000;
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if(dw_enable(c, 0) < 0)
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return -1;
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wr(c, IC_CON, CON_MASTER | CON_SLAVE_DISABLE | CON_RESTART_EN |
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(c->fast ? CON_SPEED_FAST : CON_SPEED_STD));
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// Without the firmware's numbers, periods long enough for a 150 MHz clock,
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// the fastest any of these runs at: on a slower clock the bus is merely
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// slower than it could be, never out of specification.
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if(c->fast){
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if(acpi_counts(node, "FMCN", &hcnt, &lcnt, &hold) < 0){
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hcnt = 135; // 0.6 us high, 1.3 us low, plus rise and fall
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lcnt = 240;
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}
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wr(c, IC_FS_SCL_HCNT, hcnt);
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wr(c, IC_FS_SCL_LCNT, lcnt);
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} else {
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if(acpi_counts(node, "SSCN", &hcnt, &lcnt, &hold) < 0){
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hcnt = 645; // 4.0 us high, 4.7 us low, plus the same
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lcnt = 750;
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}
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wr(c, IC_SS_SCL_HCNT, hcnt);
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wr(c, IC_SS_SCL_LCNT, lcnt);
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}
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if(hold)
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wr(c, IC_SDA_HOLD, hold);
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wr(c, IC_INTR_MASK, 0);
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wr(c, IC_RX_TL, 0);
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wr(c, IC_TX_TL, 0);
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rd(c, IC_CLR_INTR);
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return 0;
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}
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// Write `wn` bytes to `addr`, then read `rn` bytes back after a repeated
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// start, all as one transaction. 0, or -1 if the device did not answer.
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//
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// The command FIFO holds reads as well as writes, and each read becomes a
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// byte in the receive FIFO, so reads are queued no faster than they are
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// drained: a full receive FIFO stalls the bus.
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static int
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dw_xfer(struct dwi2c *c, int addr, const uchar *w, int wn, uchar *r, int rn)
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{
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int total = wn + rn, sent = 0, got = 0, spin;
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uint32 raw;
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if(dw_enable(c, 0) < 0)
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return -1;
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wr(c, IC_TAR, addr);
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rd(c, IC_CLR_INTR);
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if(dw_enable(c, 1) < 0)
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return -1;
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for(spin = 0; got < rn || sent < total; spin++){
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raw = rd(c, IC_RAW_INTR_STAT);
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if(raw & INTR_TX_ABRT)
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goto abort;
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while(got < rn && rd(c, IC_RXFLR) > 0)
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r[got++] = rd(c, IC_DATA_CMD);
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while(sent < total && (int)rd(c, IC_TXFLR) < c->txdepth){
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uint32 cmd;
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if(sent >= wn && (sent - wn) - got >= c->rxdepth)
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break;
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if(sent < wn)
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cmd = w[sent];
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else
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cmd = CMD_READ | (sent == wn && wn > 0 ? CMD_RESTART : 0);
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if(sent == total - 1)
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cmd |= CMD_STOP;
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wr(c, IC_DATA_CMD, cmd);
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sent++;
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}
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if(spin > 20000) // 200 ms: no transfer of ours takes that long
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goto abort;
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microdelay(10);
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}
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for(spin = 0; !(rd(c, IC_RAW_INTR_STAT) & INTR_STOP_DET); spin++){
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if(rd(c, IC_RAW_INTR_STAT) & INTR_TX_ABRT)
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goto abort;
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if(spin > 2000)
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goto abort;
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microdelay(10);
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}
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rd(c, IC_CLR_STOP_DET);
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dw_enable(c, 0);
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return 0;
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abort:
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rd(c, IC_TX_ABRT_SOURCE);
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rd(c, IC_CLR_TX_ABRT);
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rd(c, IC_CLR_INTR);
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dw_enable(c, 0);
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return -1;
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}
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// ---------------------------------------------------------------------------
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// ACPI
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// ---------------------------------------------------------------------------
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struct found {
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uint64 mem; // the first memory range
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int i2c, addr;
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uint32 speed;
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char bus[64]; // the controller's namespace path
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int gpio, pin, active_low;
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char gpioctl[64];
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};
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static void
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copy_source(char *dst, const uacpi_resource_source *s)
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{
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int n = s->string && s->length ? s->length : 0;
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if(n > 63)
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n = 63;
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if(n)
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memmove(dst, s->string, n);
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dst[n] = 0;
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}
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static uacpi_iteration_decision
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take_resource(void *user, uacpi_resource *r)
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{
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struct found *f = user;
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switch(r->type){
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case UACPI_RESOURCE_TYPE_FIXED_MEMORY32:
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if(!f->mem) f->mem = r->fixed_memory32.address;
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break;
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case UACPI_RESOURCE_TYPE_MEMORY32:
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if(!f->mem) f->mem = r->memory32.minimum;
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break;
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case UACPI_RESOURCE_TYPE_ADDRESS32:
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if(!f->mem && r->address32.common.type == UACPI_RANGE_MEMORY)
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f->mem = r->address32.minimum;
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break;
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case UACPI_RESOURCE_TYPE_ADDRESS64:
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if(!f->mem && r->address64.common.type == UACPI_RANGE_MEMORY)
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f->mem = r->address64.minimum;
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break;
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case UACPI_RESOURCE_TYPE_SERIAL_I2C_CONNECTION:
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if(!f->i2c){
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f->i2c = 1;
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f->addr = r->i2c_connection.slave_address;
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f->speed = r->i2c_connection.connection_speed;
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copy_source(f->bus, &r->i2c_connection.common.source);
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}
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break;
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case UACPI_RESOURCE_TYPE_GPIO_CONNECTION:
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if(!f->gpio && r->gpio_connection.type == UACPI_GPIO_CONNECTION_INTERRUPT &&
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r->gpio_connection.pin_table_length > 0){
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f->gpio = 1;
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f->pin = r->gpio_connection.pin_table[0];
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f->active_low = r->gpio_connection.intr.polarity != UACPI_POLARITY_ACTIVE_HIGH;
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copy_source(f->gpioctl, &r->gpio_connection.source);
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}
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break;
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}
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return UACPI_ITERATION_DECISION_CONTINUE;
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}
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static int
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resources(uacpi_namespace_node *node, struct found *f)
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{
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memset(f, 0, sizeof(*f));
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return uacpi_for_each_device_resource(node, "_CRS", take_resource, f) ==
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UACPI_STATUS_OK ? 0 : -1;
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}
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// The I2C-HID _DSM, function 1: the HID descriptor's register.
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static int
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hid_desc_register(uacpi_namespace_node *node, uint32 *reg)
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{
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static const uchar uuid[16] = { // 3CDFF6F7-4267-4555-AD05-B30A3D8938DE
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0xF7, 0xF6, 0xDF, 0x3C, 0x67, 0x42, 0x55, 0x45,
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0xAD, 0x05, 0xB3, 0x0A, 0x3D, 0x89, 0x38, 0xDE,
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};
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uacpi_data_view view = { .const_bytes = uuid, .length = sizeof(uuid) };
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uacpi_object_array none = { 0, 0 };
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uacpi_object *args[4], *ret = 0;
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uacpi_object_array a = { args, 4 };
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uacpi_u64 v = 0;
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int rc = -1, i;
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args[0] = uacpi_object_create_buffer(view);
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args[1] = uacpi_object_create_integer(1); // revision
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args[2] = uacpi_object_create_integer(1); // function
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args[3] = uacpi_object_create_package(none);
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if(args[0] && args[1] && args[2] && args[3] &&
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uacpi_eval(node, "_DSM", &a, &ret) == UACPI_STATUS_OK && ret &&
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uacpi_object_get_integer(ret, &v) == UACPI_STATUS_OK){
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*reg = v;
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rc = 0;
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}
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if(ret)
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uacpi_object_unref(ret);
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for(i = 0; i < 4; i++)
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if(args[i])
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uacpi_object_unref(args[i]);
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return rc;
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}
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static uacpi_namespace_node *
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node_at(const char *path)
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{
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uacpi_namespace_node *n = 0;
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if(path[0] == 0 ||
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uacpi_namespace_node_find(0, path, &n) != UACPI_STATUS_OK)
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return 0;
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return n;
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}
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static struct dwi2c *
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controller(const char *path, uint32 speed)
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{
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uacpi_namespace_node *node = node_at(path);
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struct found f;
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struct dwi2c *c;
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int i;
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if(node == 0 || resources(node, &f) < 0 || f.mem == 0){
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cprintf("i2c: no registers for controller %s\n", path);
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return 0;
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}
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for(i = 0; i < nctl; i++)
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if(ctls[i].phys == f.mem)
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return &ctls[i];
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if(nctl == NCTL)
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return 0;
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uacpi_execute(node, "_PS0", 0);
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c = &ctls[nctl];
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memset(c, 0, sizeof(*c));
|
||||
c->phys = f.mem;
|
||||
if(dw_init(c, node, speed) < 0)
|
||||
return 0;
|
||||
nctl++;
|
||||
cprintf("i2c: %s at 0x%lx, %s mode, FIFOs %d/%d\n", path, c->phys,
|
||||
c->fast ? "fast" : "standard", c->txdepth, c->rxdepth);
|
||||
return c;
|
||||
}
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
// HID over I2C
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
#define NI2CHID 4
|
||||
|
||||
struct i2chid {
|
||||
struct dwi2c *c;
|
||||
int addr;
|
||||
uint32 cmdreg, inreg, maxin;
|
||||
volatile uint32 *pin; // the interrupt pin's register, or 0
|
||||
int active_low;
|
||||
void *hid;
|
||||
uchar *buf; // one page, for input reports
|
||||
char name[8];
|
||||
};
|
||||
|
||||
static struct i2chid devs[NI2CHID];
|
||||
static int ndev;
|
||||
|
||||
static int
|
||||
reg_write(struct i2chid *d, const uchar *w, int n)
|
||||
{
|
||||
return dw_xfer(d->c, d->addr, w, n, 0, 0);
|
||||
}
|
||||
|
||||
static int
|
||||
reg_read(struct i2chid *d, uint32 reg, uchar *r, int n)
|
||||
{
|
||||
uchar w[2] = { reg & 0xFF, reg >> 8 };
|
||||
return dw_xfer(d->c, d->addr, w, 2, r, n);
|
||||
}
|
||||
|
||||
// SET_POWER and RESET, the two commands needed: written to the command
|
||||
// register as (register, opcode byte, power state / report byte).
|
||||
static int
|
||||
command(struct i2chid *d, int opcode, int arg)
|
||||
{
|
||||
uchar w[4] = { d->cmdreg & 0xFF, d->cmdreg >> 8, arg, opcode };
|
||||
return reg_write(d, w, 4);
|
||||
}
|
||||
|
||||
#define OP_RESET 0x01
|
||||
#define OP_SET_POWER 0x08
|
||||
|
||||
static void
|
||||
wait_ticks(uint n)
|
||||
{
|
||||
acquire(&tickslock);
|
||||
uint start = ticks;
|
||||
while(ticks - start < n)
|
||||
sleep(&ticks, &tickslock);
|
||||
release(&tickslock);
|
||||
}
|
||||
|
||||
// AMD's GPIO controller: one 32-bit register per pin, its level in bit 16.
|
||||
#define AMD_PIN_STS (1u << 16)
|
||||
|
||||
static int
|
||||
asserted(struct i2chid *d)
|
||||
{
|
||||
int high = (*d->pin & AMD_PIN_STS) != 0;
|
||||
return d->active_low ? !high : high;
|
||||
}
|
||||
|
||||
static volatile uint32 *
|
||||
interrupt_pin(const struct found *f)
|
||||
{
|
||||
static const char *const amd[] = { "AMDI0030", "AMD0030", 0 };
|
||||
uacpi_namespace_node *node = node_at(f->gpioctl);
|
||||
struct found g;
|
||||
|
||||
if(!f->gpio || node == 0 || !uacpi_device_matches_pnp_id(node, amd))
|
||||
return 0;
|
||||
if(resources(node, &g) < 0 || g.mem == 0)
|
||||
return 0;
|
||||
return (volatile uint32 *)((char *)ioremap(g.mem, 0x1000) + f->pin * 4);
|
||||
}
|
||||
|
||||
// One input report: two bytes of length, length included, then the report.
|
||||
// A length of 0 is the device saying it has nothing, or acknowledging a
|
||||
// reset.
|
||||
static int
|
||||
read_input(struct i2chid *d)
|
||||
{
|
||||
int len;
|
||||
|
||||
if(dw_xfer(d->c, d->addr, 0, 0, d->buf, d->maxin) < 0)
|
||||
return -1;
|
||||
len = d->buf[0] | (d->buf[1] << 8);
|
||||
if(len <= 2 || len > (int)d->maxin)
|
||||
return 0;
|
||||
hid_attached_input(d->hid, d->buf + 2, len - 2);
|
||||
return 1;
|
||||
}
|
||||
|
||||
static uacpi_iteration_decision
|
||||
probe(void *user, uacpi_namespace_node *node, uacpi_u32 depth)
|
||||
{
|
||||
struct i2chid *d;
|
||||
struct found f;
|
||||
uchar desc[30], *rdesc;
|
||||
uint32 descreg, rlen, rreg;
|
||||
int i;
|
||||
|
||||
(void)user;
|
||||
(void)depth;
|
||||
if(ndev == NI2CHID)
|
||||
return UACPI_ITERATION_DECISION_BREAK;
|
||||
d = &devs[ndev];
|
||||
memset(d, 0, sizeof(*d));
|
||||
memmove(d->name, uacpi_namespace_node_name(node).text, 4);
|
||||
|
||||
if(resources(node, &f) < 0 || !f.i2c){
|
||||
cprintf("i2c-hid: %s has no I2C connection\n", d->name);
|
||||
return UACPI_ITERATION_DECISION_CONTINUE;
|
||||
}
|
||||
if(hid_desc_register(node, &descreg) < 0){
|
||||
cprintf("i2c-hid: %s: _DSM gave no descriptor register\n", d->name);
|
||||
return UACPI_ITERATION_DECISION_CONTINUE;
|
||||
}
|
||||
if((d->c = controller(f.bus, f.speed)) == 0)
|
||||
return UACPI_ITERATION_DECISION_CONTINUE;
|
||||
d->addr = f.addr;
|
||||
uacpi_execute(node, "_PS0", 0);
|
||||
|
||||
if(reg_read(d, descreg, desc, sizeof(desc)) < 0 ||
|
||||
(desc[0] | desc[1] << 8) != 30){
|
||||
cprintf("i2c-hid: %s at 0x%x does not answer\n", d->name, d->addr);
|
||||
return UACPI_ITERATION_DECISION_CONTINUE;
|
||||
}
|
||||
rlen = desc[4] | desc[5] << 8;
|
||||
rreg = desc[6] | desc[7] << 8;
|
||||
d->inreg = desc[8] | desc[9] << 8;
|
||||
d->maxin = desc[10] | desc[11] << 8;
|
||||
d->cmdreg = desc[16] | desc[17] << 8;
|
||||
if(d->maxin < 3 || d->maxin > PGSIZE || rlen == 0 || rlen > PGSIZE){
|
||||
cprintf("i2c-hid: %s: unusable descriptor\n", d->name);
|
||||
return UACPI_ITERATION_DECISION_CONTINUE;
|
||||
}
|
||||
d->pin = interrupt_pin(&f);
|
||||
d->active_low = f.active_low;
|
||||
|
||||
command(d, OP_SET_POWER, 0); // 0 = on
|
||||
wait_ticks(2);
|
||||
command(d, OP_RESET, 0);
|
||||
wait_ticks(10);
|
||||
d->buf = (uchar *)kalloc();
|
||||
rdesc = (uchar *)kalloc();
|
||||
if(d->buf == 0 || rdesc == 0)
|
||||
return UACPI_ITERATION_DECISION_BREAK;
|
||||
// The reset is acknowledged with an empty report. Read it, and anything
|
||||
// else already waiting, so the first real report is not behind it.
|
||||
for(i = 0; i < 4 && (d->pin == 0 || asserted(d)); i++)
|
||||
if(dw_xfer(d->c, d->addr, 0, 0, d->buf, d->maxin) < 0)
|
||||
break;
|
||||
|
||||
if(reg_read(d, rreg, rdesc, rlen) < 0){
|
||||
cprintf("i2c-hid: %s: report descriptor unreadable\n", d->name);
|
||||
kfree((char *)rdesc);
|
||||
return UACPI_ITERATION_DECISION_CONTINUE;
|
||||
}
|
||||
char what[24] = "i2c-hid ";
|
||||
memmove(what + 8, d->name, 4);
|
||||
d->hid = hid_attach(rdesc, rlen, what);
|
||||
kfree((char *)rdesc);
|
||||
if(d->hid == 0){
|
||||
cprintf("i2c-hid: %s is neither a keyboard nor a pointer\n", d->name);
|
||||
return UACPI_ITERATION_DECISION_CONTINUE;
|
||||
}
|
||||
cprintf("i2c-hid: %s: %04x:%04x at 0x%x, %s\n", d->name,
|
||||
desc[20] | desc[21] << 8, desc[22] | desc[23] << 8, d->addr,
|
||||
d->pin ? "interrupt pin watched" : "polled");
|
||||
ndev++;
|
||||
return UACPI_ITERATION_DECISION_CONTINUE;
|
||||
}
|
||||
|
||||
static void
|
||||
i2c_hid_thread(void)
|
||||
{
|
||||
static const char *const ids[] = { "PNP0C50", "ACPI0C50", 0 };
|
||||
int i, n;
|
||||
|
||||
uacpi_find_devices_at(uacpi_namespace_root(), ids, probe, 0);
|
||||
if(ndev == 0)
|
||||
for(;;)
|
||||
wait_ticks(1000000);
|
||||
|
||||
for(;;){
|
||||
wait_ticks(1);
|
||||
for(i = 0; i < ndev; i++){
|
||||
struct i2chid *d = &devs[i];
|
||||
if(d->pin == 0){
|
||||
read_input(d);
|
||||
continue;
|
||||
}
|
||||
// Everything waiting, up to a bound so that a stuck line cannot keep
|
||||
// the other devices from their turn.
|
||||
for(n = 0; n < 16 && asserted(d); n++)
|
||||
if(read_input(d) < 0)
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
i2c_hid_start(void)
|
||||
{
|
||||
if(acpi_rsdp_phys() == 0)
|
||||
return;
|
||||
if(kthread_create(i2c_hid_thread, "i2chid") < 0)
|
||||
cprintf("i2c-hid: no thread; touchpads will not work\n");
|
||||
}
|
||||
Loading…
Reference in a new issue