SchOS/include/acpi.h
Nexoniarz 93f981c7ea acpi: uACPI, for interrupt routing, the power button and power-off
The firmware's AML is now interpreted. uACPI 6.1.1 (MIT) is fetched by
ports/uacpi, checksum-verified, and compiled into the kernel unmodified,
the same way lwIP is. kernel/acpi/host.c is its host layer: memory,
mapping, port and PCI config I/O, time, mutexes and events that spin
before the scheduler exists, the SCI, and an "acpi" thread for the
work the SCI defers.

PCI interrupts go where the board says. pci_init() now routes every
device's INTx through the root bridge's _PRT before drivers bind. It
follows link devices' _CRS, uses a bridge's own _PRT where the namespace
has one, and swizzles through bridges that don't. Before this, INTx
waited on the 8259's line number, which is the wrong pin in APIC mode.
irq_register() takes a trigger mode rather than a level/low flag,
because q35's links and most SCIs are level, active-high. The MADT's
interrupt source overrides are now parsed, and are what places the SCI.

The power button syncs the filesystems and powers off. shutdown() and
reboot() go through the firmware's S5 and reset register first, and
only then fall back to the emulators' ports, which a real board does
not answer.

Tested under QEMU: q35 with MSI off routes xHCI to GSI 22,
level/active-high, and it takes real interrupts with nothing polled.
system_powerdown powers off q35 and i440fx (QEMU exits 0), and q35
with 4 CPUs boots from NVMe with USB hot-plug working alongside.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01S1giNvrHTrPMPw7V6x1kQ4
2026-10-22 16:12:28 +02:00

33 lines
1.5 KiB
C

// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
// ACPI, in two layers.
//
// kernel/arch/x86_64/acpi.c reads the static tables at boot, before anything
// else can run: the MADT for the processors and the I/O APIC and its
// interrupt source overrides, the FADT for the PM timer.
//
// kernel/acpi/ is everything that needs AML, which is the firmware's own code
// and has to be interpreted: uACPI (ports/uacpi) runs it, and aml.c uses it
// for PCI interrupt routing, the power button, power-off and reset. Every
// function below that depends on it does nothing, and says so by returning
// -1, on a machine whose AML could not be loaded.
// The RSDP's physical address, or 0 if there is none.
uint64 acpi_rsdp_phys(void);
// The GSI an ISA IRQ is wired to, after the MADT's interrupt source
// overrides, and its trigger mode (an IRQ_* from irq.h) in *mode. `dflt` is
// the mode when the override says "conforms to the bus" or there is none:
// edge/high for an ISA device, level/low for the SCI.
int acpi_isa_gsi(int isa, int dflt, int *mode);
// Load and initialize the namespace. After kinit, before pci_init.
void acpi_aml_init(void);
// The worker thread that runs AML on behalf of interrupts. After sinit.
void acpi_thread_start(void);
// Route every PCI device's INTx through _PRT. From pci_init, before binding.
void acpi_pci_route(void);
int acpi_poweroff(void); // S5; returns only on failure
int acpi_reboot(void); // the FADT reset register; ditto