d0f7acf9eb
An x86-64 operating system built from xv6, now largely rewritten: SMP, a copy-on-write root filesystem (SchFS), PCI/USB/virtio drivers, a TTF rasteriser, and a Linux-numbered syscall ABI. No history before this point -- the tree was never under version control. This commit exists so the rename that follows has something to undo to.
165 lines
6.6 KiB
C
165 lines
6.6 KiB
C
#pragma once
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// Intel 8254x gigabit Ethernet — the register and descriptor layout.
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//
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// From Intel's public "PCI/PCI-X Family of Gigabit Ethernet Controllers
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// Software Developer's Manual" (317453). A public document with no licence on
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// what you write from it, which is why this is written rather than ported: see
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// docs/licensing.md and docs/roadmap.md §1.
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//
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// QEMU's `-device e1000` is an 82540EM and implements enough of the manual to
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// be worth targeting; it is also what the default `-net nic` gives you.
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#define E1000_VENDOR 0x8086
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// The 8254x family: PCI/PCI-X gigabit controllers that share the register map,
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// descriptor format and EEPROM interface this driver implements.
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//
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// The device IDs are transcribed from FreeBSD's `sys/dev/e1000/e1000_hw.h`
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// (Copyright (c) 2001-2020, Intel Corporation, BSD 3-clause -- verified to
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// carry no advertising clause; see docs/licensing.md and NOTICE). They are
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// data, not logic: the driver below is still written from Intel's manual
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// 317453, and nothing of FreeBSD's implementation is used.
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//
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// This matters more than it looks. The driver bound exactly one device -- the
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// 82540EM QEMU emulates -- which is fine for a virtual machine and useless on
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// the sort of second-hand hardware a system like this actually gets run on.
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// These are the cards in every desktop and server of that generation.
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//
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// Deliberately *not* included: the PCIe 8257x parts (82571-82574) and anything
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// newer. They present a similar register map but differ in NVM access and
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// initialisation, and claiming a device this driver has not been shown to
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// initialise is worse than not claiming it -- the card binds, reports a MAC of
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// nonsense, and nothing works for reasons that look nothing like the cause.
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#define E1000_DEV_82540EM 0x100E
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#define E1000_DEV_82540EM_LOM 0x1015
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#define E1000_DEV_82540EP_LOM 0x1016
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#define E1000_DEV_82540EP 0x1017
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#define E1000_DEV_82540EP_LP 0x101E
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#define E1000_DEV_82541EI 0x1013
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#define E1000_DEV_82541EI_MOBILE 0x1018
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#define E1000_DEV_82541ER_LOM 0x1014
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#define E1000_DEV_82541ER 0x1078
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#define E1000_DEV_82541GI 0x1076
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#define E1000_DEV_82541GI_MOBILE 0x1077
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#define E1000_DEV_82541GI_LF 0x107C
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#define E1000_DEV_82544EI_FIBER 0x1009
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#define E1000_DEV_82544GC_COPPER 0x100C
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#define E1000_DEV_82544GC_LOM 0x100D
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#define E1000_DEV_82545EM_COPPER 0x100F
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#define E1000_DEV_82545EM_FIBER 0x1011
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#define E1000_DEV_82545GM_COPPER 0x1026
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#define E1000_DEV_82545GM_FIBER 0x1027
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#define E1000_DEV_82545GM_SERDES 0x1028
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#define E1000_DEV_82546EB_COPPER 0x1010
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#define E1000_DEV_82546EB_FIBER 0x1012
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#define E1000_DEV_82546EB_QUAD 0x101D
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#define E1000_DEV_82546GB_COPPER 0x1079
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#define E1000_DEV_82546GB_FIBER 0x107A
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#define E1000_DEV_82546GB_SERDES 0x107B
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#define E1000_DEV_82547EI 0x1019
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// --- registers, byte offsets into BAR 0 ------------------------------------
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#define E1000_CTRL 0x0000 // device control
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#define E1000_STATUS 0x0008 // device status
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#define E1000_EERD 0x0014 // EEPROM read
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#define E1000_ICR 0x00C0 // interrupt cause read
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#define E1000_IMS 0x00D0 // interrupt mask set
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#define E1000_IMC 0x00D8 // interrupt mask clear
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#define E1000_RCTL 0x0100 // receive control
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#define E1000_TCTL 0x0400 // transmit control
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#define E1000_TIPG 0x0410 // transmit inter-packet gap
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#define E1000_RDBAL 0x2800 // receive descriptor base, low
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#define E1000_RDBAH 0x2804 // receive descriptor base, high
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#define E1000_RDLEN 0x2808 // receive descriptor length, in bytes
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#define E1000_RDH 0x2810 // receive descriptor head
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#define E1000_RDT 0x2818 // receive descriptor tail
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#define E1000_TDBAL 0x3800
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#define E1000_TDBAH 0x3804
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#define E1000_TDLEN 0x3808
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#define E1000_TDH 0x3810
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#define E1000_TDT 0x3818
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#define E1000_MTA 0x5200 // multicast table array, 128 entries
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#define E1000_RAL 0x5400 // receive address low (the MAC filter)
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#define E1000_RAH 0x5404 // receive address high
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// CTRL
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#define E1000_CTRL_RST (1 << 26)
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#define E1000_CTRL_ASDE (1 << 5) // auto-speed detection
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#define E1000_CTRL_SLU (1 << 6) // set link up
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// STATUS
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#define E1000_STATUS_LU (1 << 1) // link up
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// EERD
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#define E1000_EERD_START (1 << 0)
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#define E1000_EERD_DONE (1 << 4)
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#define E1000_EERD_ADDR_SHIFT 8
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#define E1000_EERD_DATA_SHIFT 16
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// RCTL
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#define E1000_RCTL_EN (1 << 1) // receiver enable
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#define E1000_RCTL_SBP (1 << 2) // store bad packets
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#define E1000_RCTL_UPE (1 << 3) // unicast promiscuous
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#define E1000_RCTL_MPE (1 << 4) // multicast promiscuous
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#define E1000_RCTL_LBM_NONE (0 << 6)
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#define E1000_RCTL_BAM (1 << 15) // accept broadcast
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#define E1000_RCTL_SZ_2048 (0 << 16) // buffer size, with BSEX clear
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#define E1000_RCTL_SECRC (1 << 26) // strip the Ethernet CRC
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// TCTL
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#define E1000_TCTL_EN (1 << 1)
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#define E1000_TCTL_PSP (1 << 3) // pad short packets
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#define E1000_TCTL_CT_SHIFT 4 // collision threshold
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#define E1000_TCTL_COLD_SHIFT 12 // collision distance
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// Transmit descriptor command bits
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#define E1000_TXD_CMD_EOP (1 << 0) // end of packet
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#define E1000_TXD_CMD_IFCS (1 << 1) // insert FCS/CRC
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#define E1000_TXD_CMD_RS (1 << 3) // report status
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#define E1000_TXD_STAT_DD (1 << 0) // descriptor done
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// Receive descriptor status bits
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#define E1000_RXD_STAT_DD (1 << 0)
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#define E1000_RXD_STAT_EOP (1 << 1)
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// Interrupt causes worth unmasking.
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#define E1000_ICR_TXDW (1 << 0) // transmit descriptor written back
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#define E1000_ICR_LSC (1 << 2) // link status change
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#define E1000_ICR_RXDMT0 (1 << 4) // receive descriptor minimum threshold
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#define E1000_ICR_RXT0 (1 << 7) // receiver timer
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// --- descriptors -----------------------------------------------------------
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//
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// Both are 16 bytes and the hardware reads them by physical address, so the
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// rings must be physically contiguous and 16-byte aligned.
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struct e1000_tx_desc {
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uint64 addr;
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uint16 length;
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uint8 cso; // checksum offset
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uint8 cmd;
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uint8 status;
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uint8 css; // checksum start
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uint16 special;
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} __attribute__((packed));
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struct e1000_rx_desc {
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uint64 addr;
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uint16 length;
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uint16 checksum;
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uint8 status;
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uint8 errors;
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uint16 special;
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} __attribute__((packed));
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// Ring sizes. The manual requires the descriptor ring length to be a multiple
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// of 128 bytes, i.e. a multiple of 8 descriptors.
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#define E1000_NTX 16
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#define E1000_NRX 16
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#define E1000_BUFSZ 2048
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