a1c965da1e
Sixty-five headers sat side by side in include/, so `#include "irq.h"` said nothing about where irq.h was or what it belonged to, and errno.h, stat.h and fcntl.h at the top shadowed the system's for any host tool built with -I./include. They are in folders now -- arch/ core/ fs/ dev/ gfx/ net/ uapi/ (and ldls/ for the Linux driver layer) -- and every include names the folder, as Linux's do: "core/proc.h". Done mechanically and checked the hard way: the kernel built from this tree disassembles identically to the one built from the tree before it. The full image boots, and userland is the same set of programs. Paths in docs and comments follow; docs/guides/layout.md has a table of what is where, and tools/fix-includes.py rewrites old-style includes from the folders in the tree, for code written before this. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01S1giNvrHTrPMPw7V6x1kQ4
119 lines
3.7 KiB
C
119 lines
3.7 KiB
C
// The I/O APIC manages hardware interrupts for an SMP system.
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// http://www.intel.com/design/chipsets/datashts/29056601.pdf
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// See also picirq.c.
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#include "core/types.h"
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#include "core/defs.h"
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#include "arch/traps.h"
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#include "arch/memlayout.h"
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#include "arch/mmu.h"
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#include "arch/mp.h"
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#include "core/param.h"
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#include "core/proc.h"
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#define REG_ID 0x00 // Register index: ID
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#define REG_VER 0x01 // Register index: version
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#define REG_TABLE 0x10 // Redirection table base
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// The redirection table starts at REG_TABLE and uses
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// two registers to configure each interrupt.
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// The first (low) register in a pair contains configuration bits.
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// The second (high) register contains a bitmask telling which
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// CPUs can serve that interrupt.
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#define INT_DISABLED 0x00010000 // Interrupt disabled
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#define INT_LEVEL 0x00008000 // Level-triggered (vs edge-)
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#define INT_ACTIVELOW 0x00002000 // Active low (vs high)
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#define INT_LOGICAL 0x00000800 // Destination is CPU id (vs APIC ID)
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volatile struct ioapic *ioapic;
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// IO APIC MMIO structure: write reg, then read or write data.
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struct ioapic {
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uint reg;
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uint pad[3];
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uint data;
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};
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static uint
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ioapicread(int reg)
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{
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ioapic->reg = reg;
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return ioapic->data;
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}
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static void
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ioapicwrite(int reg, uint data)
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{
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ioapic->reg = reg;
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ioapic->data = data;
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}
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void
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ioapicinit(void)
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{
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int i, id, maxintr;
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// The firmware's address for it, not a constant: see ioapic_phys in mp.c.
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// ioremap() rather than P2V because nothing obliges it to be in the low
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// four gigabytes the direct map is sure to cover.
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ioapic = ioremap(ioapic_phys, PGSIZE);
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if(!ioapic)
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panic("ioapicinit: cannot map the I/O APIC");
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maxintr = (ioapicread(REG_VER) >> 16) & 0xFF;
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id = ioapicread(REG_ID) >> 24;
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if(id != ioapicid)
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cprintf("ioapicinit: id isn't equal to ioapicid; not a MP\n");
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// Mark all interrupts edge-triggered, active high, disabled,
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// and not routed to any CPUs.
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for(i = 0; i <= maxintr; i++){
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ioapicwrite(REG_TABLE+2*i, INT_DISABLED | (T_IRQ0 + i));
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ioapicwrite(REG_TABLE+2*i+1, 0);
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}
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}
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// Route an interrupt to a CPU and unmask it.
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//
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// `level_low` picks PCI's signalling instead of ISA's. This distinction did
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// not matter while every interrupt in the kernel came from an ISA-era device
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// at a fixed pin, all of which are edge-triggered and active high -- which is
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// why the original ioapicenable() hardcoded exactly that. A PCI device wired
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// through an INTx pin is the opposite on both counts, and configuring it as
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// edge/high does not fail cleanly: the device raises the line, we take one
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// interrupt, and because the level never goes away there is no second edge
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// and the device is never heard from again.
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void
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ioapicroute(int irq, int cpunum, int level_low)
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{
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uint lo = T_IRQ0 + irq;
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// A mode from include/core/irq.h; 1, the PCI case, is what `level_low` meant
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// when it was a flag.
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if(level_low == 1 || level_low == 2)
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lo |= INT_LEVEL;
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if(level_low == 1 || level_low == 3)
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lo |= INT_ACTIVELOW;
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// Program the destination before unmasking, so the entry is never briefly
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// live pointing at CPU 0 when it was meant for another.
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//
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// The destination is an APIC *ID*, not a CPU index. This wrote the index,
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// which is the same number only when the boot processor's APIC ID is 0 --
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// true under every emulator and on most boards, and not promised: an
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// interrupt aimed at an ID nobody has is an interrupt nobody receives.
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ioapicwrite(REG_TABLE+2*irq+1, (uint)cpus[cpunum].apicid << 24);
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ioapicwrite(REG_TABLE+2*irq, lo);
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}
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void
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ioapicmask(int irq)
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{
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ioapicwrite(REG_TABLE+2*irq, INT_DISABLED | (T_IRQ0 + irq));
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}
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void
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ioapicenable(int irq, int cpunum)
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{
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ioapicroute(irq, cpunum, 0);
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}
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