7e8d5e2821
PCI drivers took their interrupt from INTERRUPT_LINE. On real hardware that is the 8259's number, not the IOAPIC pin the device is wired to (that is in ACPI _PRT, which needs AML), so nothing ever arrived. xHCI is entirely interrupt-driven, so the USB keyboard and a USB root would have hung even on a clean boot. Under QEMU the two numbers agree, which is why it never showed. - pci_irq_attach()/pci_irq_detach(): MSI, then MSI-X if the driver allows it, then INTx. The handler is registered before MSI is enabled, so no edge is lost. xHCI, e1000, r8169 and rtl8139 use it. - Lines 24-29 are MSI vectors. The LAPIC error vector moves from 19, which is a PCI pin on Intel chipsets, to 30. Nothing is placed at or above vector 64 (T_SYSCALL). - A storming line is masked and its handlers are polled instead of being left to eat the CPU. A level line that has had a handler for 2 s and never fired is polled every tick by a kernel thread. Tested in QEMU q35 with the root on a USB stick: xHCI and e1000e on MSI; then MSI disabled and INTx deliberately misrouted, where xHCI got zero interrupts and the root still mounted through the poller. i440fx INTx and the rtl8139 hand-over are unchanged. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01HH7xukt4aaiGj1nQEAoQf1
60 lines
2.7 KiB
C
60 lines
2.7 KiB
C
#pragma once
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// Hardware interrupt registration.
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//
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// Until this existed, trap() was a switch statement listing every interrupt
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// the kernel knew about, and adding a device meant editing the trap handler.
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// That is fine while the devices are the four the PC has always had at fixed
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// pins; it stops being fine the moment a device's IRQ is whatever the BIOS
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// decided to put in its PCI config space this boot. A driver cannot write
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// `case T_IRQ0 + IRQ_XHCI:` because there is no such constant -- it only
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// learns its line at probe time.
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//
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// So: a line has a chain of handlers, a driver adds itself to one at probe
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// time, and enabling the line is a consequence of registering rather than a
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// separate call somebody can forget.
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//
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// Chains matter more than they look. PCI interrupt pins are *shared*: four
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// INTx lines are routed to a handful of IOAPIC inputs, so two unrelated
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// devices routinely land on the same one. A handler must therefore check
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// whether its own device actually raised the interrupt and do nothing if it
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// did not.
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// Lines 0-23 are the IOAPIC's pins. 24-29 are MSI vectors, which are not pins
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// at all -- a device writes the vector number to the local APIC directly --
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// and are dispatched through the same table so that a handler cannot tell
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// which kind it is on. 30 and 31 are the LAPIC's error and spurious vectors.
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// Everything stops below vector 64, which is T_SYSCALL: a line there would
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// let a user-mode `int $0x40` dispatch an interrupt and EOI one that is not.
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#define NIRQ_IOAPIC 24
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#define IRQ_MSI_FIRST 24
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#define IRQ_MSI_LAST 29
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#define NIRQ 31
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#define NCHAIN 4 // handlers that may share one line
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typedef void (*irq_handler_t)(void *arg);
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// Returns 0, or -1 if the line is out of range, reserved, or full.
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// Registering enables the line; the last unregister masks it again.
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//
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// `level_low` selects PCI's signalling (level-triggered, active low) rather
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// than ISA's (edge-triggered, active high). Getting this wrong does not fail
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// cleanly: an edge-configured level interrupt fires once and then wedges,
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// because the device keeps the line asserted and no further edge ever comes.
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int irq_register(int irq, irq_handler_t fn, void *arg, const char *name,
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int level_low);
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void irq_unregister(int irq, irq_handler_t fn, void *arg);
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int irq_handler_count(int irq);
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// Called from trap() with the IOAPIC pin number, not the vector.
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void irq_dispatch(int irq);
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void irq_init(void);
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// An MSI vector for pci_irq_attach(). -1 when all six are in use.
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int irq_alloc_msi(void);
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void irq_free_msi(int irq);
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// The thread that polls PCI lines which never interrupt. After sinit().
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void irq_poll_start(void);
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int irq_info(char *buf, int cap); // /proc/interrupts
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