93f981c7ea
The firmware's AML is now interpreted. uACPI 6.1.1 (MIT) is fetched by ports/uacpi, checksum-verified, and compiled into the kernel unmodified, the same way lwIP is. kernel/acpi/host.c is its host layer: memory, mapping, port and PCI config I/O, time, mutexes and events that spin before the scheduler exists, the SCI, and an "acpi" thread for the work the SCI defers. PCI interrupts go where the board says. pci_init() now routes every device's INTx through the root bridge's _PRT before drivers bind. It follows link devices' _CRS, uses a bridge's own _PRT where the namespace has one, and swizzles through bridges that don't. Before this, INTx waited on the 8259's line number, which is the wrong pin in APIC mode. irq_register() takes a trigger mode rather than a level/low flag, because q35's links and most SCIs are level, active-high. The MADT's interrupt source overrides are now parsed, and are what places the SCI. The power button syncs the filesystems and powers off. shutdown() and reboot() go through the firmware's S5 and reset register first, and only then fall back to the emulators' ports, which a real board does not answer. Tested under QEMU: q35 with MSI off routes xHCI to GSI 22, level/active-high, and it takes real interrupts with nothing polled. system_powerdown powers off q35 and i440fx (QEMU exits 0), and q35 with 4 CPUs boots from NVMe with USB hot-plug working alongside. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01S1giNvrHTrPMPw7V6x1kQ4
70 lines
3.2 KiB
C
70 lines
3.2 KiB
C
#pragma once
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// Hardware interrupt registration.
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//
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// Until this existed, trap() was a switch statement listing every interrupt
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// the kernel knew about, and adding a device meant editing the trap handler.
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// That is fine while the devices are the four the PC has always had at fixed
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// pins; it stops being fine the moment a device's IRQ is whatever the BIOS
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// decided to put in its PCI config space this boot. A driver cannot write
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// `case T_IRQ0 + IRQ_XHCI:` because there is no such constant -- it only
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// learns its line at probe time.
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//
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// So: a line has a chain of handlers, a driver adds itself to one at probe
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// time, and enabling the line is a consequence of registering rather than a
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// separate call somebody can forget.
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//
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// Chains matter more than they look. PCI interrupt pins are *shared*: four
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// INTx lines are routed to a handful of IOAPIC inputs, so two unrelated
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// devices routinely land on the same one. A handler must therefore check
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// whether its own device actually raised the interrupt and do nothing if it
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// did not.
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// Lines 0-23 are the IOAPIC's pins. 24-29 are MSI vectors, which are not pins
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// at all -- a device writes the vector number to the local APIC directly --
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// and are dispatched through the same table so that a handler cannot tell
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// which kind it is on. 30 and 31 are the LAPIC's error and spurious vectors.
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// Everything stops below vector 64, which is T_SYSCALL: a line there would
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// let a user-mode `int $0x40` dispatch an interrupt and EOI one that is not.
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#define NIRQ_IOAPIC 24
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#define IRQ_MSI_FIRST 24
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#define IRQ_MSI_LAST 29
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#define NIRQ 31
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#define NCHAIN 4 // handlers that may share one line
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typedef void (*irq_handler_t)(void *arg);
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// Returns 0, or -1 if the line is out of range, reserved, or full.
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// Registering enables the line; the last unregister masks it again.
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//
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// `level_low` selects PCI's signalling (level-triggered, active low) rather
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// than ISA's (edge-triggered, active high). Getting this wrong does not fail
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// cleanly: an edge-configured level interrupt fires once and then wedges,
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// because the device keeps the line asserted and no further edge ever comes.
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//
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// It is a mode, not a flag. 0 and 1 are the two above, which is all a PCI or
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// ISA device needs; the other two are what ACPI can say about a line -- q35's
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// PCI links and most machines' SCI are level-triggered *active high*, and
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// programming one active low leaves the pin reading as permanently asserted.
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#define IRQ_EDGE_HIGH 0 // ISA
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#define IRQ_LEVEL_LOW 1 // PCI INTx
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#define IRQ_LEVEL_HIGH 2
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#define IRQ_EDGE_LOW 3
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#define IRQ_IS_LEVEL(m) ((m) == IRQ_LEVEL_LOW || (m) == IRQ_LEVEL_HIGH)
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int irq_register(int irq, irq_handler_t fn, void *arg, const char *name,
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int level_low);
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void irq_unregister(int irq, irq_handler_t fn, void *arg);
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int irq_handler_count(int irq);
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// Called from trap() with the IOAPIC pin number, not the vector.
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void irq_dispatch(int irq);
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void irq_init(void);
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// An MSI vector for pci_irq_attach(). -1 when all six are in use.
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int irq_alloc_msi(void);
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void irq_free_msi(int irq);
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// The thread that polls PCI lines which never interrupt. After sinit().
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void irq_poll_start(void);
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int irq_info(char *buf, int cap); // /proc/interrupts
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