d0f7acf9eb
An x86-64 operating system built from xv6, now largely rewritten: SMP, a copy-on-write root filesystem (SchFS), PCI/USB/virtio drivers, a TTF rasteriser, and a Linux-numbered syscall ABI. No history before this point -- the tree was never under version control. This commit exists so the rename that follows has something to undo to.
161 lines
6.7 KiB
C
161 lines
6.7 KiB
C
#pragma once
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// eXtensible Host Controller Interface -- the register and data-structure
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// definitions from the xHCI 1.2 specification.
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//
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// Why xHCI and not UHCI/OHCI/EHCI: xHCI is the only host controller interface
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// that speaks every USB speed, so one driver covers USB 1.1 through 3.x. The
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// older controllers would each need their own, and a machine with all of them
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// needs the companion-controller handover dance on top. There is no hardware
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// worth supporting that has no xHCI.
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// ---------------------------------------------------------------------------
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// Capability registers -- at the start of BAR0, read-only
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// ---------------------------------------------------------------------------
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#define XHCI_CAPLENGTH 0x00 // byte: where the operational regs begin
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#define XHCI_HCIVERSION 0x02 // word
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#define XHCI_HCSPARAMS1 0x04
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#define XHCI_HCSPARAMS2 0x08
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#define XHCI_HCSPARAMS3 0x0C
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#define XHCI_HCCPARAMS1 0x10
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#define XHCI_DBOFF 0x14 // doorbell array offset from BAR0
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#define XHCI_RTSOFF 0x18 // runtime register offset from BAR0
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#define HCS1_MAXSLOTS(x) ((x) & 0xFF)
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#define HCS1_MAXINTRS(x) (((x) >> 8) & 0x7FF)
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#define HCS1_MAXPORTS(x) (((x) >> 24) & 0xFF)
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// Scratchpad buffer count is split across two fields, high part first.
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#define HCS2_SPB_HI(x) (((x) >> 21) & 0x1F)
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#define HCS2_SPB_LO(x) (((x) >> 27) & 0x1F)
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#define HCC1_AC64 (1 << 0) // 64-bit addressing
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#define HCC1_CSZ (1 << 2) // contexts are 64 bytes, not 32
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#define HCC1_XECP(x) (((x) >> 16) & 0xFFFF) // extended caps, in dwords
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// ---------------------------------------------------------------------------
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// Operational registers -- at BAR0 + CAPLENGTH
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// ---------------------------------------------------------------------------
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#define XHCI_USBCMD 0x00
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#define XHCI_USBSTS 0x04
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#define XHCI_PAGESIZE 0x08
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#define XHCI_DNCTRL 0x14
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#define XHCI_CRCR 0x18 // 64-bit
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#define XHCI_DCBAAP 0x30 // 64-bit
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#define XHCI_CONFIG 0x38
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#define XHCI_PORTSC(p) (0x400 + 0x10 * ((p) - 1)) // ports are 1-based
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#define CMD_RS (1 << 0) // run/stop
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#define CMD_HCRST (1 << 1) // host controller reset
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#define CMD_INTE (1 << 2) // interrupter enable
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#define CMD_HSEE (1 << 3)
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#define STS_HCH (1 << 0) // halted
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#define STS_HSE (1 << 2) // host system error
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#define STS_EINT (1 << 3) // event interrupt (write 1 to clear)
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#define STS_PCD (1 << 4) // port change detect (write 1 to clear)
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#define STS_CNR (1 << 11) // controller not ready
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#define CRCR_RCS (1 << 0) // ring cycle state
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// PORTSC. The change bits are write-1-to-clear, and so is PED -- writing back
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// a value read from this register clears whatever happened to be set. Every
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// write has to mask them off first.
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#define PORT_CCS (1 << 0) // current connect status
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#define PORT_PED (1 << 1) // port enabled (RW1C!)
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#define PORT_OCA (1 << 3)
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#define PORT_PR (1 << 4) // port reset
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#define PORT_PLS(x) (((x) >> 5) & 0xF)
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#define PORT_PP (1 << 9) // port power
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#define PORT_SPEED(x) (((x) >> 10) & 0xF)
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#define PORT_CSC (1 << 17)
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#define PORT_PEC (1 << 18)
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#define PORT_PRC (1 << 21)
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#define PORT_RW1C 0x00FE0002u // change bits 17..23, plus PED
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// PORTSC speed encoding. These are the same numbers as USB_SPEED_* in usb.h,
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// which is not a coincidence -- the core uses this encoding directly so that
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// nothing has to be translated on its way to a slot context.
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#define XSPEED_FULL USB_SPEED_FULL
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#define XSPEED_LOW USB_SPEED_LOW
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#define XSPEED_HIGH USB_SPEED_HIGH
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#define XSPEED_SUPER USB_SPEED_SUPER
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// ---------------------------------------------------------------------------
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// Runtime registers -- at BAR0 + RTSOFF. Interrupter n is at 0x20 + 32*n.
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// ---------------------------------------------------------------------------
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#define XHCI_MFINDEX 0x00
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#define XHCI_IR0 0x20
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#define IR_IMAN 0x00
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#define IR_IMOD 0x04
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#define IR_ERSTSZ 0x08
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#define IR_ERSTBA 0x10 // 64-bit
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#define IR_ERDP 0x18 // 64-bit
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#define IMAN_IP (1 << 0) // interrupt pending (RW1C)
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#define IMAN_IE (1 << 1) // interrupt enable
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#define ERDP_EHB (1 << 3) // event handler busy (RW1C)
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// ---------------------------------------------------------------------------
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// Transfer Request Blocks
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// ---------------------------------------------------------------------------
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struct trb {
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uint64 param;
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uint32 status;
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uint32 control;
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} __attribute__((packed));
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#define TRB_TYPE(t) (((t) & 0x3F) << 10)
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#define TRB_GET_TYPE(c) (((c) >> 10) & 0x3F)
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#define TRB_C (1 << 0) // cycle bit
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#define TRB_TC (1 << 1) // toggle cycle (link TRBs)
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#define TRB_ISP (1 << 2)
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#define TRB_CH (1 << 4) // chain
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#define TRB_IOC (1 << 5) // interrupt on completion
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#define TRB_IDT (1 << 6) // immediate data
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#define TRB_SLOT(s) ((uint32)(s) << 24)
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#define TRB_GET_SLOT(c) (((c) >> 24) & 0xFF)
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#define TRB_GET_EPID(c) (((c) >> 16) & 0x1F) // transfer events
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// Transfer TRBs
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#define TRB_NORMAL 1
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#define TRB_SETUP 2
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#define TRB_DATA 3
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#define TRB_STATUS 4
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#define TRB_LINK 6
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// Command TRBs
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#define TRB_ENABLE_SLOT 9
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#define TRB_DISABLE_SLOT 10
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#define TRB_ADDRESS_DEV 11
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#define TRB_CONFIG_EP 12
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#define TRB_EVAL_CTX 13
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#define TRB_RESET_EP 14
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#define TRB_NOOP_CMD 23
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// Event TRBs
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#define TRB_XFER_EVENT 32
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#define TRB_CMD_COMPLETE 33
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#define TRB_PORT_STATUS 34
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#define TRB_CC(status) (((status) >> 24) & 0xFF)
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#define CC_SUCCESS 1
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#define CC_SHORT_PACKET 13
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// Setup Stage transfer type, and Data Stage direction.
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#define TRT_NONE 0
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#define TRT_OUT 2
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#define TRT_IN 3
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#define DIR_IN (1 << 16)
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// Endpoint types in an endpoint context. Direction is part of the type, and
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// the numbering is not arbitrary: OUT types are 1-3, control is 4, and the IN
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// types are the OUT ones plus four.
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#define EPTYPE_ISOCH_OUT 1
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#define EPTYPE_BULK_OUT 2
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#define EPTYPE_INT_OUT 3
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#define EPTYPE_CONTROL 4
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#define EPTYPE_ISOCH_IN 5
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#define EPTYPE_BULK_IN 6
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#define EPTYPE_INT_IN 7
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// Doorbell targets: 0 is the command ring; for a device slot, DCI 1 is EP0.
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#define DCI_EP0 1
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