boot: stop assuming the machine is an emulator
Every one of these works under QEMU and stops a real machine:
- MADT processors that are "online capable" but not enabled were
counted as CPUs. AMD firmware lists absent cores that way (so does
QEMU with maxcpus), and startothers() then waited for ever for an
AP that does not exist. Only enabled entries count now, x2APIC
(type 9) entries are read too, and the wait is bounded to a second;
an AP that misses it is parked with INIT and the boot goes on.
- The PIT calibration loop had no bound. Recent boards clock-gate the
8254: the output never rises (a hang) or floats high (TSC "0 MHz"
and every clock thousands of times fast). The loop is bounded and
checked, and falls back to the ACPI PM timer, then CPUID 0x15/0x16.
Under QEMU pit=off the PM timer gives the same figures the PIT did.
- Firmware that hands over in x2APIC mode left lapic[] reading
garbage: cpunum() panicked or the timer never started. Each CPU is
switched back to xAPIC first (x2APIC -> disabled -> xAPIC).
- The IOAPIC was always at 0xFEC00000 and interrupts were aimed at
APIC ID "0". Both now come from the firmware's tables.
- INIT-to-STARTUP was 100 us ("Bochs is slow"); it is the 10 ms the
MP specification asks for.
- mouseinit() drained the 8042 with an unbounded loop. With no
controller the port reads 0xFF and the loop never ends. It now
notices there is no controller and skips the mouse.
Tested in QEMU: i440fx and q35, -smp 4, -smp 2,maxcpus=4, pit=off.
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01HH7xukt4aaiGj1nQEAoQf1
This commit is contained in:
Nexoniarz
parent
f1798e7443
commit
94c936ed98
7 changed files with 355 additions and 23 deletions
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@ -28,6 +28,13 @@
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extern struct cpu cpus[NCPU];
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extern int ncpu;
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extern uchar ioapicid;
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extern uint64 ioapic_phys;
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// The ACPI power-management timer: a 3.579545 MHz counter at an I/O port the
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// FADT names. 0 when there is none. lapic.c times the TSC against it when the
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// PIT does not count -- see calibrate_without_pit().
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uint32 acpi_pmtmr_port;
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int acpi_pmtmr_32; // 32 bits wide rather than 24
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extern volatile uint *lapic;
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// The Root System Description Pointer. Found by signature, not by being told
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@ -73,6 +80,7 @@ struct acpi_madt {
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#define MADT_LAPIC 0
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#define MADT_IOAPIC 1
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#define MADT_LAPIC_OVERRIDE 5
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#define MADT_X2APIC 9
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struct madt_entry {
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uint8 type;
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@ -97,6 +105,18 @@ struct madt_ioapic {
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uint32 gsi_base;
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} __attribute__((packed));
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// The same as MADT_LAPIC, for a processor whose APIC ID does not fit in a
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// byte -- or whose firmware simply prefers this form. Firmware that hands over
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// in x2APIC mode is entitled to describe every processor this way and none
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// the old way, and then a parser that reads only type 0 finds no CPUs at all.
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struct madt_x2apic {
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struct madt_entry e;
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uint16 reserved;
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uint32 apic_id;
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uint32 flags;
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uint32 acpi_uid;
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} __attribute__((packed));
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struct madt_lapic_override {
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struct madt_entry e;
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uint16 reserved;
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@ -211,6 +231,36 @@ find_table(struct acpi_rsdp *rsdp, const char *sig)
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}
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// Returns 1 if the processors were enumerated, 0 to fall back to mpinit().
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// One processor from the MADT.
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//
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// Enabled processors only. "Online capable" means the processor is *not*
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// running but could be brought up later by hot-plug, which this kernel does
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// not do -- and AMD firmware routinely lists every core the socket could have
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// that way, present or not. Counting those as CPUs sent startothers() a
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// STARTUP to an APIC that does not exist, and then it waited for an answer
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// for ever: a hang after "acpi: N cpus" on exactly the machines whose table
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// was the most complete.
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//
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// An ID above 254 is refused too: xAPIC addresses a processor with eight bits
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// (255 is broadcast), and that is the mode this kernel runs the APIC in.
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static void
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add_cpu(uint32 apic_id, uint32 flags)
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{
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if (!(flags & LAPIC_ENABLED))
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return;
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if (apic_id > 254) {
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cprintf("acpi: cpu with apic id %u needs x2APIC; not using it\n", apic_id);
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return;
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}
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for (int i = 0; i < ncpu; i++)
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if (cpus[i].apicid == apic_id)
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return; // listed as both type 0 and type 9
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if (ncpu < NCPU) {
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cpus[ncpu].apicid = (uchar)apic_id;
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ncpu++;
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}
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}
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int
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acpi_init(void)
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{
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@ -218,6 +268,17 @@ acpi_init(void)
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if (!rsdp)
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return 0;
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// The FADT first, for the PM timer: PM_TMR_BLK at offset 76, and bit 8 of
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// the flags at 112 says whether it counts 32 bits or 24. A hardware-reduced
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// platform has neither and says so with a zero port.
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struct acpi_sdt *fadt = find_table(rsdp, "FACP");
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if (fadt && fadt->length >= 116 && checksum_ok(fadt, fadt->length)) {
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acpi_pmtmr_port = *(uint32 *)((uint8 *)fadt + 76);
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acpi_pmtmr_32 = (*(uint32 *)((uint8 *)fadt + 112) >> 8) & 1;
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if (acpi_pmtmr_port > 0xFFFF)
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acpi_pmtmr_port = 0;
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}
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struct acpi_madt *madt = (struct acpi_madt *)find_table(rsdp, "APIC");
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if (!madt || !checksum_ok(madt, madt->h.length))
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return 0;
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@ -239,23 +300,28 @@ acpi_init(void)
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switch (ent->type) {
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case MADT_LAPIC: {
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struct madt_lapic *l = (struct madt_lapic *)p;
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// Skip processors that are neither enabled nor online-capable: those are
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// sockets the firmware is describing but not offering.
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if (!(l->flags & (LAPIC_ENABLED | LAPIC_ONLINE_CAPABLE)))
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break;
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if (ncpu < NCPU) {
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cpus[ncpu].apicid = l->apic_id;
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ncpu++;
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}
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add_cpu(l->apic_id, l->flags);
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break;
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}
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case MADT_X2APIC: {
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struct madt_x2apic *x = (struct madt_x2apic *)p;
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add_cpu(x->apic_id, x->flags);
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break;
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}
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case MADT_IOAPIC: {
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struct madt_ioapic *io = (struct madt_ioapic *)p;
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// The first one only. Multi-I/O-APIC routing needs the interrupt source
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// overrides too, which nothing here reads yet, so claiming to support it
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// would be worse than not.
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if (!found_ioapic) {
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// One only: the one whose inputs start at GSI 0, which is where the ISA
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// lines and the chipset's PCI lines are. Multi-I/O-APIC routing needs
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// the interrupt source overrides too, which nothing here reads yet, so
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// claiming to support it would be worse than not.
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//
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// And its address from the table rather than 0xFEC00000. That is the
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// usual place and not a promised one: a second I/O APIC listed first,
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// or a board that moved the first, used to get its registers written
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// at an address where there were none.
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if (!found_ioapic || io->gsi_base == 0) {
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ioapicid = io->id;
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ioapic_phys = io->addr;
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found_ioapic = 1;
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}
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break;
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@ -6,8 +6,11 @@
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#include "defs.h"
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#include "traps.h"
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#include "memlayout.h"
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#include "mmu.h"
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#include "mp.h"
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#include "param.h"
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#include "proc.h"
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#define IOAPIC 0xFEC00000 // Default physical address of IO APIC
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#define REG_ID 0x00 // Register index: ID
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#define REG_VER 0x01 // Register index: version
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@ -51,7 +54,12 @@ ioapicinit(void)
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{
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int i, id, maxintr;
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ioapic = P2V((volatile struct ioapic*)IOAPIC);
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// The firmware's address for it, not a constant: see ioapic_phys in mp.c.
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// ioremap() rather than P2V because nothing obliges it to be in the low
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// four gigabytes the direct map is sure to cover.
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ioapic = ioremap(ioapic_phys, PGSIZE);
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if(!ioapic)
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panic("ioapicinit: cannot map the I/O APIC");
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maxintr = (ioapicread(REG_VER) >> 16) & 0xFF;
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id = ioapicread(REG_ID) >> 24;
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if(id != ioapicid)
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@ -85,7 +93,12 @@ ioapicroute(int irq, int cpunum, int level_low)
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// Program the destination before unmasking, so the entry is never briefly
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// live pointing at CPU 0 when it was meant for another.
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ioapicwrite(REG_TABLE+2*irq+1, cpunum << 24);
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//
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// The destination is an APIC *ID*, not a CPU index. This wrote the index,
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// which is the same number only when the boot processor's APIC ID is 0 --
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// true under every emulator and on most boards, and not promised: an
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// interrupt aimed at an ID nobody has is an interrupt nobody receives.
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ioapicwrite(REG_TABLE+2*irq+1, (uint)cpus[cpunum].apicid << 24);
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ioapicwrite(REG_TABLE+2*irq, lo);
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}
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@ -80,6 +80,116 @@ uint lapic_timer_hz; // measured LAPIC timer counts per second
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uint64 tsc_hz; // measured TSC cycles per second
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uint64 boot_tsc; // the TSC when calibration finished
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// The TSC's frequency from the processor itself, for when there is no PIT to
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// time it against. 0 if the processor does not say.
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//
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// Leaf 0x15 is the ratio of the TSC to the core crystal, and the crystal's
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// frequency when the part reports it; leaf 0x16 is the base frequency in MHz,
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// which is the TSC's on every part that has an invariant one. The first is
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// exact and the second is a nominal figure, so the first is preferred.
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static uint64
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tsc_hz_from_cpuid(void)
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{
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uint32 max, a, b, c, d;
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cpuid_leaf(0, &max, 0, 0, 0);
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if (max >= 0x15) {
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cpuid_leaf(0x15, &a, &b, &c, &d);
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if (a && b && c)
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return (uint64)c * b / a;
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}
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if (max >= 0x16) {
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cpuid_leaf(0x16, &a, 0, 0, 0);
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if (a & 0xFFFF)
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return (uint64)(a & 0xFFFF) * 1000000;
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}
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return 0;
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}
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// The fallback when the PIT does not count.
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//
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// Something else has to be the stopwatch. In order: the ACPI PM timer, which
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// is a real clock at a fixed 3.579545 MHz on every PC that is not
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// hardware-reduced; then the TSC frequency the processor states in CPUID,
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// with the TSC itself as the stopwatch; and only then a guess.
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extern uint32 acpi_pmtmr_port;
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extern int acpi_pmtmr_32;
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#define PMTMR_HZ 3579545
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// 50 ms of the PM timer, with the LAPIC and the TSC counted across it.
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// Returns 0 if the timer did not move, which is a port that is not one.
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static int
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calibrate_pmtimer(void)
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{
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uint32 mask = acpi_pmtmr_32 ? 0xFFFFFFFFu : 0x00FFFFFFu;
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uint32 want = PMTMR_HZ / 20, t0, t;
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lapicw(TDCR, X1);
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lapicw(TIMER, MASKED);
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lapicw(TICR, 0xFFFFFFFF);
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t0 = inl(acpi_pmtmr_port) & mask;
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uint64 tsc0 = rdtsc();
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uint lap0 = lapic[TCCR];
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do {
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t = inl(acpi_pmtmr_port) & mask;
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if (rdtsc() - tsc0 > 4000000000ULL) {
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lapicw(TICR, 0);
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return 0;
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}
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} while (((t - t0) & mask) < want);
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uint lap1 = lapic[TCCR];
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uint64 tsc1 = rdtsc();
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lapicw(TICR, 0);
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uint32 ticks = (t - t0) & mask;
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tsc_hz = (tsc1 - tsc0) * PMTMR_HZ / ticks;
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lapic_timer_hz = (uint)((uint64)(lap0 - lap1) * PMTMR_HZ / ticks);
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boot_tsc = tsc1;
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return tsc_hz >= 20000000ULL;
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}
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static void
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calibrate_without_pit(void)
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{
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if (acpi_pmtmr_port && calibrate_pmtimer()) {
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kinfo("cpu0: the PIT does not count; timed against the ACPI PM timer\n");
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} else {
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tsc_hz = tsc_hz_from_cpuid();
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if (tsc_hz == 0) {
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// Nothing left to measure against. Wrong-but-running, as below: time
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// will run at the wrong speed and the line says that it may.
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tsc_hz = 2000000000ULL;
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cprintf("cpu0: no PIT, no PM timer and no TSC frequency from CPUID; "
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"assuming 2 GHz\n");
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} else {
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kinfo("cpu0: the PIT does not count; TSC frequency from CPUID\n");
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}
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lapicw(TDCR, X1);
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lapicw(TIMER, MASKED);
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lapicw(TICR, 0xFFFFFFFF);
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uint64 tsc0 = rdtsc();
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uint lap0 = lapic[TCCR];
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uint64 until = tsc0 + tsc_hz / 20; // 50 ms
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while (rdtsc() < until)
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asm volatile("pause");
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uint lap1 = lapic[TCCR];
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uint64 tsc1 = rdtsc();
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lapicw(TICR, 0);
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lapic_timer_hz = (uint)((uint64)(lap0 - lap1) * tsc_hz / (tsc1 - tsc0));
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boot_tsc = tsc1;
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}
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if (lapic_timer_hz < HZ * 1000u) {
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cprintf("cpu0: lapic calibration implausible (%u Hz), assuming 1 GHz bus\n",
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lapic_timer_hz);
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lapic_timer_hz = 1000000000u;
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}
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}
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static void
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calibrate_timers(void)
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{
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@ -105,12 +215,41 @@ calibrate_timers(void)
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uint64 tsc0 = rdtsc();
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uint lap0 = lapic[TCCR];
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while (!(inb(PIT_GATE) & 0x20)) // ch2 output rises at terminal count
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;
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// Bounded. "Always present" stopped being true: recent Intel boards
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// clock-gate the 8254 to save power, and then the output never rises and
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// this loop was the whole of the boot -- a machine stopped at the line
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// before "lapic timer", with nothing to say why. Four billion TSC cycles is
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// over a second on anything that exists and twenty times the window on a
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// 4 GHz part, so a working PIT never comes near it.
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//
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// And checked at the start: in mode 0 the output goes low the moment the
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// count is written, so a bit that is already high is no PIT at all. An
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// absent one floats -- port 0x61 reads 0xFF -- and then the loop ended at
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// once, the TSC was "measured" at 0 MHz, and every clock in the system ran
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// thousands of times fast. Under QEMU with pit=off uptime read four days
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// thirty seconds after boot.
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int pit_ok = !(inb(PIT_GATE) & 0x20);
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while (pit_ok && !(inb(PIT_GATE) & 0x20)) { // ch2 output rises at terminal count
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if (rdtsc() - tsc0 > 4000000000ULL) {
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pit_ok = 0;
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break;
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}
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}
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uint lap1 = lapic[TCCR];
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uint64 tsc1 = rdtsc();
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// 50 ms of a TSC slower than 20 MHz is no processor this runs on: the
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// window was not 50 ms, so the PIT was not counting it.
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if (pit_ok && tsc1 - tsc0 < 1000000)
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pit_ok = 0;
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if (!pit_ok) {
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lapicw(TICR, 0);
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calibrate_without_pit();
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return;
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}
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lapicw(TICR, 0); // stop counting
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// TCCR counts down, so elapsed counts are start minus end.
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@ -134,12 +273,61 @@ calibrate_timers(void)
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}
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}
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#define MSR_APIC_BASE 0x1B
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#define APIC_BASE_EN (1ULL << 11) // globally enabled
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#define APIC_BASE_EXTD (1ULL << 10) // x2APIC mode
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// Put this processor's local APIC in xAPIC mode, which is the mode everything
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// here speaks: registers at an MMIO address, read and written as memory.
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//
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// Firmware is allowed to hand over in x2APIC mode, and on recent Intel
|
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// laptops it usually does. In that mode the MMIO page is not the APIC any
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// more -- the registers are MSRs -- so every lapic[] access read nothing
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// useful: the ID came back wrong, cpunum() panicked "unknown apicid", and the
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// timer was never started. A hang or a panic within the first second, on the
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// newest machines and on no emulator, because none of them hand over that way.
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//
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// The architecture allows exactly one way back: x2APIC to disabled, disabled
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// to xAPIC. Disabling discards the APIC's state, which costs nothing here
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// because lapicinit() is about to set all of it.
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//
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// It cannot be done when the processor has locked xAPIC out (some server
|
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// parts, which report it in IA32_XAPIC_DISABLE_STATUS), or when its APIC ID
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// does not fit in eight bits. Both get said plainly rather than left to fail
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// at the first register access.
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void
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lapic_xapic_mode(void)
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{
|
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uint32 d;
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uint64 base = rdmsr(MSR_APIC_BASE);
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if ((base & (APIC_BASE_EN | APIC_BASE_EXTD)) == APIC_BASE_EN)
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return; // xAPIC already: the usual case
|
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|
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if (base & APIC_BASE_EXTD) {
|
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cpuid_leaf(7, 0, 0, 0, &d);
|
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if (d & (1u << 29)) { // IA32_ARCH_CAPABILITIES exists
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uint64 caps = rdmsr(0x10A);
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if ((caps & (1ULL << 21)) && (rdmsr(0xBD) & 1))
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panic("lapic: firmware has locked the APIC in x2APIC mode");
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}
|
||||
if (rdmsr(0x802) > 254) // x2APIC ID register
|
||||
panic("lapic: APIC id too large for xAPIC mode");
|
||||
wrmsr(MSR_APIC_BASE, base & ~(APIC_BASE_EN | APIC_BASE_EXTD));
|
||||
}
|
||||
// From disabled (whether firmware left it so or the line above did) to
|
||||
// xAPIC. The base address bits are kept: they are where lapic[] points.
|
||||
wrmsr(MSR_APIC_BASE, (base & ~APIC_BASE_EXTD) | APIC_BASE_EN);
|
||||
}
|
||||
|
||||
void
|
||||
lapicinit(void)
|
||||
{
|
||||
if(!lapic)
|
||||
return;
|
||||
|
||||
lapic_xapic_mode();
|
||||
|
||||
// Enable local APIC; set spurious interrupt vector.
|
||||
lapicw(SVR, ENABLE | (T_IRQ0 + IRQ_SPURIOUS));
|
||||
|
||||
|
|
@ -281,7 +469,11 @@ lapicstartap(uchar apicid, uint addr)
|
|||
lapicw(ICRLO, SINIT | LEVEL | ASSERT);
|
||||
microdelay(200);
|
||||
lapicw(ICRLO, SINIT | LEVEL);
|
||||
microdelay(100); // should be 10ms, but too slow in Bochs!
|
||||
// The MP specification's 10 ms. This was 100 us, "because Bochs is slow",
|
||||
// which is a figure for an emulator: older real processors want the full
|
||||
// wait between INIT and STARTUP, and starting one too early is an AP that
|
||||
// does not come up.
|
||||
microdelay(10000);
|
||||
|
||||
// Send startup IPI (twice!) to enter code.
|
||||
// Regular hardware is supposed to only accept a STARTUP
|
||||
|
|
@ -295,6 +487,20 @@ lapicstartap(uchar apicid, uint addr)
|
|||
}
|
||||
}
|
||||
|
||||
// Hold a processor in wait-for-SIPI. For an AP that did not report in on
|
||||
// time: if it is merely slow, this stops it from waking later and reading the
|
||||
// trampoline parameters startothers() has since written for the next one --
|
||||
// which would be two processors on one stack.
|
||||
void
|
||||
lapic_park(uchar apicid)
|
||||
{
|
||||
lapicw(ICRHI, apicid<<24);
|
||||
lapicw(ICRLO, SINIT | LEVEL | ASSERT);
|
||||
microdelay(200);
|
||||
lapicw(ICRLO, SINIT | LEVEL);
|
||||
microdelay(100);
|
||||
}
|
||||
|
||||
#define CMOS_STATA 0x0a
|
||||
#define CMOS_STATB 0x0b
|
||||
#define CMOS_UIP (1 << 7) // RTC update in progress
|
||||
|
|
|
|||
|
|
@ -25,6 +25,9 @@ int ncpu;
|
|||
// working ones, which was a comfortable thing to read and false.
|
||||
int ncpu_online = 1;
|
||||
uchar ioapicid;
|
||||
// Where the I/O APIC's registers are. Every source that describes it -- the
|
||||
// MADT, or this table -- says so, and ioapicinit() maps whatever they said.
|
||||
uint64 ioapic_phys = IOAPIC_DEFAULT_PHYS;
|
||||
|
||||
static uchar
|
||||
sum(uchar *addr, int len)
|
||||
|
|
@ -116,7 +119,9 @@ mpinit(void)
|
|||
switch(*p){
|
||||
case MPPROC:
|
||||
mproc = (struct mpproc*)p;
|
||||
if(ncpu < NCPU) {
|
||||
// Bit 0 is "usable". A disabled entry is a processor that is not
|
||||
// there, and starting it means waiting for an answer that never comes.
|
||||
if((mproc->flags & 0x01) && ncpu < NCPU) {
|
||||
cpus[ncpu].apicid = mproc->apicid; // apicid may differ from ncpu
|
||||
ncpu++;
|
||||
}
|
||||
|
|
@ -124,7 +129,10 @@ mpinit(void)
|
|||
continue;
|
||||
case MPIOAPIC:
|
||||
ioapic = (struct mpioapic*)p;
|
||||
ioapicid = ioapic->apicno;
|
||||
if(ioapic_phys == IOAPIC_DEFAULT_PHYS || ioapic->addr_p == IOAPIC_DEFAULT_PHYS){
|
||||
ioapicid = ioapic->apicno;
|
||||
ioapic_phys = ioapic->addr_p;
|
||||
}
|
||||
p += sizeof(struct mpioapic);
|
||||
continue;
|
||||
case MPBUS:
|
||||
|
|
|
|||
Loading…
Reference in a new issue